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1. 发明授权

US09071040B2 Ion generator 有权
标题翻译：离子发生器
公开(公告)号：US09071040B2
公开(公告)日：2015-06-30
申请号：US13812955
申请日：2011-06-10
申请人： Toshio Mamiya , Masato Urushisaki , Takashi Nakabayashi
发明人： Toshio Mamiya , Masato Urushisaki , Takashi Nakabayashi
IPC分类号： H01T23/00 , F24F3/16 , A61L9/22
CPC分类号： H01T23/00 , A61L9/22 , F24F3/166 , F24F2003/1682
摘要： A partition is formed between an ion generating unit at the windward side and an ion generating unit at the leeward side, so that the amount of airflow to pass through the ion generating unit at the windward side will become more in comparison to the amount of airflow to pass through the ion generating unit at the leeward side.
摘要翻译：在迎风侧的离子产生单元和背风侧的离子产生单元之间形成隔板，使得与迎风侧相比，通过离子产生单元的气流量将变得更大在背风侧通过离子产生单元。

2. 发明申请

US20130126749A1 ION GENERATOR 有权
标题翻译：离子发生器
公开(公告)号：US20130126749A1
公开(公告)日：2013-05-23
申请号：US13812955
申请日：2011-06-10
申请人： Toshio Mamiya , Masato Urushisaki , Takashi Nakabayashi
发明人： Toshio Mamiya , Masato Urushisaki , Takashi Nakabayashi
IPC分类号： H01T23/00
CPC分类号： H01T23/00 , A61L9/22 , F24F3/166 , F24F2003/1682
摘要： A partition is formed between an ion generating unit at the windward side and an ion generating unit at the leeward side, so that the amount of airflow to pass through the ion generating unit at the windward side will become more in comparison to the amount of airflow to pass through the ion generating unit at the leeward side.
摘要翻译：在迎风侧的离子产生单元和背风侧的离子产生单元之间形成隔板，使得与迎风侧相比，通过离子产生单元的气流量将变得更大在背风侧通过离子产生单元。

3. 发明授权

US07795662B2 Semiconductor memory device and method for fabricating same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07795662B2
公开(公告)日：2010-09-14
申请号：US11822921
申请日：2007-07-11
申请人： Hideyuki Arai , Takashi Nakabayashi
发明人： Hideyuki Arai , Takashi Nakabayashi
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852 , H01L27/10888
摘要： A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and the upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.
摘要翻译：半导体存储器件具有形成在半导体衬底上并具有设置在膜中的电容器开口部分的第一层间绝缘膜，以及形成在电容器开口部分的底部和侧面上并由下部电极构成的电容元件，绝缘膜和上电极。通过第一层间绝缘膜形成位线接触插头。下电极，电容绝缘膜和位于位线接触插塞的一侧的上电极的至少一部分位于第一层间绝缘膜的表面下方，下电极，电容绝缘层膜，并且上电极位于电容器开口部分的侧面上。上电极仅形成在电容器开口部的底部和侧面上。

4. 发明授权

US07737480B2 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07737480B2
公开(公告)日：2010-06-15
申请号：US11826089
申请日：2007-07-12
申请人： Ryo Nakagawa , Takashi Nakabayashi , Hideyuki Arai
发明人： Ryo Nakagawa , Takashi Nakabayashi , Hideyuki Arai
IPC分类号： H01L31/062
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10811
摘要： A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.
摘要翻译：半导体存储器件包括：形成在衬底中的晶体管; 形成在所述晶体管的源/漏区之一上的电容器; 形成在衬底上并沿晶体管的栅极长度方向延伸的位线; 连接源极/漏极区域和电容器之一的第一导电插头; 连接到未连接到第一导电插头的另一个源极/漏极区域的第二导电插头; 以及形成在所述第二导电插头上并连接到所述位线的第三导电插塞。第三导电插塞的中心轴线在晶体管的栅极宽度方向上从第二导电插头的中心轴线移位。

5. 发明申请

US20080035975A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080035975A1
公开(公告)日：2008-02-14
申请号：US11826089
申请日：2007-07-12
申请人： Ryo Nakagawa , Takashi Nakabayashi , Hideyuki Arai
发明人： Ryo Nakagawa , Takashi Nakabayashi , Hideyuki Arai
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10811
摘要： A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.
摘要翻译：半导体存储器件包括：形成在衬底中的晶体管; 形成在所述晶体管的源/漏区之一上的电容器; 形成在衬底上并沿晶体管的栅极长度方向延伸的位线; 连接源极/漏极区域和电容器之一的第一导电插头; 连接到未连接到第一导电插头的另一个源极/漏极区域的第二导电插头; 以及形成在所述第二导电插头上并连接到所述位线的第三导电插塞。第三导电插塞的中心轴线在晶体管的栅极宽度方向上从第二导电插头的中心轴线移位。

6. 发明申请

US20080001250A1 Semiconductor device and fabrication method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080001250A1
公开(公告)日：2008-01-03
申请号：US11714900
申请日：2007-03-07
申请人： Hideo Ichimura , Takashi Nakabayashi
发明人： Hideo Ichimura , Takashi Nakabayashi
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5252 , H01L27/10811 , H01L27/10852 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a capacitor including a first lower electrode, a capacitor insulating film, and a first upper electrode which are successively formed above a substrate and a fuse element including a second lower electrode, a fuse insulating film, and a second upper electrode which are successively formed above a different region of the substrate from the region thereof on which the capacitor is formed. The first lower electrode is formed to have a depressed cross-sectional configuration. The second lower electrode has a columnar configuration and is made of the same conductive material as the first lower electrode.
摘要翻译：半导体器件具有包括依次形成在衬底上的第一下电极，电容器绝缘膜和第一上电极以及包括第二下电极，熔丝绝缘膜和第二上电极的熔丝元件的电容器，依次形成在与其上形成有电容器的区域的基板的不同区域上方。第一下电极形成为具有凹陷的横截面构造。第二下部电极具有柱状构造，并且由与第一下部电极相同的导电材料制成。

7. 发明申请

US20070275529A1 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20070275529A1
公开(公告)日：2007-11-29
申请号：US11702593
申请日：2007-02-06
申请人： Hideyuki Arai , Takashi Nakabayashi , Yasutoshi Okuno
发明人： Hideyuki Arai , Takashi Nakabayashi , Yasutoshi Okuno
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/823412 , H01L29/7833
摘要： After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then, the protective insulating film formed on the second active region is removed. Next, an insulating film to be a second gate insulating film is formed on the second active region, and then, the insulating film to be the first gate insulating film formed on the third active region is removed. Finally, an insulating film to be a third gate insulating film is formed on the third active region.
摘要翻译：在第一至第三有源区上形成保护绝缘膜之后，去除形成在第一和第三有源区上的保护绝缘膜。随后，在第一和第三有源区域中的每一个上形成作为第一栅极绝缘膜的绝缘膜，然后去除形成在第二有源区上的保护绝缘膜。接下来，在第二有源区上形成作为第二栅极绝缘膜的绝缘膜，然后除去形成在第三有源区上的作为第一栅极绝缘膜的绝缘膜。最后，在第三有源区上形成作为第三栅极绝缘膜的绝缘膜。

8. 发明申请

US20060086960A1 Semiconductor memory and method for manufacturing the same 失效
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20060086960A1
公开(公告)日：2006-04-27
申请号：US11152109
申请日：2005-06-15
申请人： Hideyuki Arai , Takashi Nakabayashi , Takashi Ohtsuka
发明人： Hideyuki Arai , Takashi Nakabayashi , Takashi Ohtsuka
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10888 , H01L28/91
摘要： A capacitor of a semiconductor memory of the present invention includes: a lower electrode which covers the surface of a storage node hole from the bottom to at least one of the sidewalls up to a level lower than the top surface of a second interlayer insulating film; a capacitive insulating film which covers the lower electrode; and an upper electrode which covers the capacitive insulating film.
摘要翻译：本发明的半导体存储器的电容器包括：下电极，其从底部到至少一个侧壁覆盖存储节点孔的表面直到比第二层间绝缘膜的顶表面低的水平; 覆盖下电极的电容绝缘膜; 以及覆盖电容绝缘膜的上电极。

9. 发明申请

US20050093089A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050093089A1
公开(公告)日：2005-05-05
申请号：US10995283
申请日：2004-11-24
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8242 , H01L29/00
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.
摘要翻译：形成了比硅衬底的有源区域更高级的隔离。在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

10. 发明授权

US06876682B2 Light generating module 有权
标题翻译：发光模块
公开(公告)号：US06876682B2
公开(公告)日：2005-04-05
申请号：US10079817
申请日：2002-02-22
申请人： Takashi Nakabayashi , Atsushi Hamakawa
发明人： Takashi Nakabayashi , Atsushi Hamakawa
IPC分类号： G02B6/42 , H01S5/022 , H01S5/026 , H01S5/042 , H01S3/04
CPC分类号： H01S5/02284 , H01L2224/48091 , H01S5/02216 , H01S5/02248 , H01S5/0427 , H01S5/06226 , H01S5/0683 , H01L2924/00014
摘要： A light generating module 1 comprises a housing 2, a semiconductor light-emitting device 4, a driving element 6, and a monitoring light-receiving device 8. The monitoring light-receiving device 8 is optically coupled with the semiconductor light-emitting device 4. The driving element 6 drives the semiconductor light-emitting device 4. The housing 2 contains the semiconductor light-emitting device 4, the driving element 6, and the monitoring light-receiving device 8. These elements 4, 6, and 8 are disposed sequentially along a predetermined axis. The driving element 6 is disposed between the semiconductor light-emitting device 4 and the monitoring light-receiving device 8. This configuration makes it possible to dispose the driving element 6 close to the semiconductor light-emitting device 4 so as to achieve a transmission rate of 10 Gbps without degrading the optical coupling between the semiconductor light-receiving device 8 and the semiconductor light-emitting device 4.
摘要翻译：发光模块1包括壳体2，半导体发光装置4，驱动元件6和监视光接收装置8.监视光接收装置8与半导体发光装置4光学耦合驱动元件6驱动半导体发光装置4.壳体2包含半导体发光装置4，驱动元件6和监视光接收装置8.这些元件4,6和8被设置顺序地沿预定轴线。驱动元件6设置在半导体发光装置4和监视光接收装置8之间。这种构造使得可以将驱动元件6配置在靠近半导体发光装置4以实现传输速率 10Gbps，而不会降低半导体光接收装置8和半导体发光装置4之间的光耦合。

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