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1. 发明授权

US07248188B2 Encoder and decoder 有权
标题翻译：编码器和解码器
公开(公告)号：US07248188B2
公开(公告)日：2007-07-24
申请号：US11377124
申请日：2006-03-16
申请人： Toshio Ito , Masaru Sawada , Toshihiko Morita
发明人： Toshio Ito , Masaru Sawada , Toshihiko Morita
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , G11B20/1866
摘要： An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.
摘要翻译：编码比特串生成单元生成通过对输入比特串进行扰频编码的比特串。直流分量评估单元在逐位移位时，选择由编码比特串生成单元生成的比特串中具有预定宽度的比特串，并且评估所选择的比特串中的直流分量。基于直流分量评估单元的评价结果，位串提取单元提取具有抑制的直流分量的比特串。

2. 发明申请

US20060220926A1 Encoder and decoder 审中-公开
标题翻译：编码器和解码器
公开(公告)号：US20060220926A1
公开(公告)日：2006-10-05
申请号：US11201895
申请日：2005-08-11
申请人： Toshio Ito , Masaru Sawada , Toshihiko Morita
发明人： Toshio Ito , Masaru Sawada , Toshihiko Morita
IPC分类号： H03M7/00
CPC分类号： G11B20/10009 , G11B20/10194 , G11B20/1426 , G11B2020/1457
摘要： An encoder includes an encoded-bit-string generating unit that generates a plurality of bit strings encoded by scrambling with respect to an input bit string; a DC-component evaluating unit that selects a bit string having a predetermined width in the bit strings generated by the encoded-bit-string generating unit, while shifting bits one by one or every m-bits, where m is a positive integer, and evaluates the DC component in each of the bit strings selected; and a bit-string extracting unit that extracts a bit string with suppressed DC component from among the bit strings encoded, based on a result of an evaluation by the direct-current-component evaluating unit.
摘要翻译：编码器包括编码比特串生成单元，其生成通过相对于输入比特串的加扰编码的多个比特串; DC分量评估单元，在由位编码比特串生成单元生成的比特串中选择具有预定宽度的比特串，同时移位比特一个或每个m比特，其中m是正整数，以及评估所选择的每个位串中的直流分量; 以及位串提取单元，其基于直流分量评估单元的评估结果，从编码的比特串中提取具有抑制的DC分量的比特串。

3. 发明授权

US07644337B2 Error correction device, encoder, decoder, method, and information storage device 有权
标题翻译：纠错装置，编码器，解码器，方法和信息存储装置
公开(公告)号：US07644337B2
公开(公告)日：2010-01-05
申请号：US11514041
申请日：2006-08-31
申请人： Toshio Ito , Toshihiko Morita
发明人： Toshio Ito , Toshihiko Morita
IPC分类号： H03M13/29
CPC分类号： H03M13/1102 , H03M13/1515 , H03M13/19 , H03M13/29 , H03M13/2918 , H03M13/2927 , H03M13/293
摘要： An encoder divides the data in which sector data is adjacently connected to a first RS parity generated in Reed Solomon encoding into blocks to and subjects each of the blocks to cyclic Hamming encoding so as to generate Hamming parities. Subsequently, the data in which the Hamming parities are aligned in a row is subjected to Reed Solomon encoding so as to generate a second RS parity, and encoded data in which the first RS parity and the second RS parity are adjacently connected to the sector data is output. A decoder s divides the sector data and the first RS parity into n blockes and cyclic Hamming encoding, aligns the parities thereof, corrects errors in the parities by Reed Solomon decoding by the second RS parity, then corrects 1-bit errors in blockes by cyclic Hamming decoding, and further corrects errors of 2 or more bits by Reed Solomon decoding by the first RS parity.
摘要翻译：编码器将哪个扇区数据相邻地连接到在Reed Solomon编码中产生的第一RS奇偶校验的数据分成块，并将每个块的每一个块进行循环汉明编码，以便产生汉明奇偶校验。随后，将汉明奇偶校验排成行的数据进行Reed Solomon编码，以产生第二RS奇偶校验，并且将第一RS奇偶校验和第二RS奇偶校验相邻连接到扇区数据的编码数据被输出。解码器将扇区数据和第一RS奇偶校验分为n个块和循环汉明编码，对齐其奇偶校验，通过Reed Solomon解码校正奇偶校验中的错误，通过第二RS奇偶校验，然后通过循环来纠正块中的1位错误汉明解码，并通过第一RS奇偶校验由Reed Solomon解码进一步校正2位或更多位的错误。

4. 发明申请

US20070266300A1 Error correction device, encoder, decoder, method, and information storage device 有权
标题翻译：纠错装置，编码器，解码器，方法和信息存储装置
公开(公告)号：US20070266300A1
公开(公告)日：2007-11-15
申请号：US11514041
申请日：2006-08-31
申请人： Toshio Ito , Toshihiko Morita
发明人： Toshio Ito , Toshihiko Morita
IPC分类号： G11C29/00
CPC分类号： H03M13/1102 , H03M13/1515 , H03M13/19 , H03M13/29 , H03M13/2918 , H03M13/2927 , H03M13/293
摘要： An encoder divides the data in which sector data is adjacently connected to a first RS parity generated in Reed Solomon encoding into blocks to and subjects each of the blocks to cyclic Hamming encoding so as to generate Hamming parities. Subsequently, the data in which the Hamming parities are aligned in a row is subjected to Reed Solomon encoding so as to generate a second RS parity, and encoded data in which the first RS parity and the second RS parity are adjacently connected to the sector data is output. A decoder divides the sector data and the first RS parity into n blockes and cyclic Hamming encoding, aligns the parities thereof, corrects errors in the parities by Reed Solomon decoding by the second RS parity, then corrects 1-bit errors in blockes by cyclic Hamming decoding, and further corrects errors of 2 or more bits by Reed Solomon decoding by the first RS parity.
摘要翻译：编码器将哪个扇区数据相邻地连接到在Reed Solomon编码中产生的第一RS奇偶校验的数据分成块，并将每个块的每一个块进行循环汉明编码，以便产生汉明奇偶校验。随后，将汉明奇偶校验排成行的数据进行Reed Solomon编码，以产生第二RS奇偶校验，并且将第一RS奇偶校验和第二RS奇偶校验相邻连接到扇区数据的编码数据被输出。解码器将扇区数据和第一RS奇偶校验分为n个块和循环汉明编码，对齐其奇偶校验，通过Reed Solomon解码校正奇偶校验中的错误，通过第二RS奇偶校验，然后通过循环汉明校正块阻塞中的1位错误解码，并通过第一RS奇偶校验通过Reed Solomon解码进一步校正2位或更多位的错误。

5. 发明申请

US20070245220A1 Error correction apparatus 有权
标题翻译：纠错装置
公开(公告)号：US20070245220A1
公开(公告)日：2007-10-18
申请号：US11509282
申请日：2006-08-24
申请人： Toshio Ito , Toshihiko Morita
发明人： Toshio Ito , Toshihiko Morita
IPC分类号： H03M13/00
CPC分类号： G11B20/1833 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/1545
摘要： One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged by using the coefficients of the error locator polynomial and the same calculation is performed for a second data string if a correction failure is judged. Contrarily, if a correction success is judged, an error of the first data string is corrected by using the aforementioned set of the syndromes and the coefficients of the error locator polynomial.
摘要翻译：从包括至少2t + 1个符号作为奇偶校验串的多个第一数据串中计算一组综合征，以及来自一组综合征的误差定位多项式的系数。通过使用误差定位多项式的系数来判断校正是否成功，如果判断出校正失败，则对第二数据串执行相同的计算。相反，如果判断校正成功，则通过使用上述的校正子集和误差定位多项式的系数来校正第一数据串的错误。

6. 发明授权

US07098818B1 Encoder and decoder using run-length-limited code 失效
标题翻译：编码器和解码器使用运行长度限制代码
公开(公告)号：US07098818B1
公开(公告)日：2006-08-29
申请号：US11166978
申请日：2005-06-24
申请人： Masaru Sawada , Toshio Ito , Toshihiko Morita
发明人： Masaru Sawada , Toshio Ito , Toshihiko Morita
IPC分类号： H03M5/00 , G06F15/00 , G06F11/00
CPC分类号： H03M5/145
摘要： When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.
摘要翻译：当从存储在第一输入寄存器1111和第二输入寄存器1112中的数据检测违反游程长度限制（RLL）代码的G约束的零运行时，将零运行之前和之后的位传送到一个临时寄存器1150通过总线进行零运行移除1130以彼此组合。因此，通过有效地利用总线传输的机制，可以简化电路，从而实现小电路。

7. 发明申请

US20060250286A1 Encoder and decoder using run-length-limited code 失效
标题翻译：编码器和解码器使用运行长度限制代码
公开(公告)号：US20060250286A1
公开(公告)日：2006-11-09
申请号：US11484003
申请日：2006-07-10
申请人： Masaru Sawada , Toshio Ito , Toshihiko Morita
发明人： Masaru Sawada , Toshio Ito , Toshihiko Morita
IPC分类号： H03M7/12
CPC分类号： H03M5/145
摘要： When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.
摘要翻译：当从存储在第一输入寄存器1111和第二输入寄存器1112中的数据检测违反游程长度限制（RLL）代码的G约束的零运行时，将零运行之前和之后的位传送到一个临时寄存器1150通过总线进行零运行移除1130以彼此组合。因此，通过有效地利用总线传输的机制，可以简化电路，从而实现小电路。

8. 发明申请

US20060220928A1 Encoder and decoder 有权
标题翻译：编码器和解码器
公开(公告)号：US20060220928A1
公开(公告)日：2006-10-05
申请号：US11377124
申请日：2006-03-16
申请人： Toshio Ito , Masaru Sawada , Toshihiko Morita
发明人： Toshio Ito , Masaru Sawada , Toshihiko Morita
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , G11B20/1866
摘要： An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.
摘要翻译：编码比特串生成单元生成通过对输入比特串进行加扰而编码的比特串。直流分量评估单元在逐位移位时，选择由编码比特串生成单元生成的比特串中具有预定宽度的比特串，并且评估所选择的比特串中的直流分量。基于直流分量评估单元的评价结果，位串提取单元提取具有抑制的直流分量的比特串。

9. 发明申请

US20050225458A1 Recording and reproducing apparatus 有权
标题翻译：记录和再现设备
公开(公告)号：US20050225458A1
公开(公告)日：2005-10-13
申请号：US10982610
申请日：2004-11-05
申请人： Toshio Ito , Masaru Sawada , Toshihiko Morita , Takao Sugawara
发明人： Toshio Ito , Masaru Sawada , Toshihiko Morita , Takao Sugawara
IPC分类号： G11B20/10 , G11B5/09 , G11B20/14 , G11B20/18 , H03M5/14 , H03M7/14 , H03M7/00
CPC分类号： H03M5/145 , G11B20/1426
摘要： A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.
摘要翻译：记录和再现装置包括将信息位串编码为码位串的RLL编码器和将码位串解码为信息位串的RLL解码器。 RLL编码器以满足关于连续零串的多个约束条件的高编码率将信息位串编码为游程长度受限码的码位串。 RLL解码器将由RLL编码器编码的码位串解码为信息位串。

10. 发明授权

US07793197B2 Error correction apparatus 有权
标题翻译：纠错装置
公开(公告)号：US07793197B2
公开(公告)日：2010-09-07
申请号：US11509282
申请日：2006-08-24
申请人： Toshio Ito , Toshihiko Morita
发明人： Toshio Ito , Toshihiko Morita
IPC分类号： H03M13/00
CPC分类号： G11B20/1833 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/1545
摘要： One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged by using the coefficients of the error locator polynomial and the same calculation is performed for a second data string if a correction failure is judged. Contrarily, if a correction success is judged, an error of the first data string is corrected by using the aforementioned set of the syndromes and the coefficients of the error locator polynomial.
摘要翻译：从包括至少2t + 1个符号作为奇偶校验串的多个第一数据串中计算一组综合征，以及来自一组综合征的误差定位多项式的系数。通过使用误差定位多项式的系数来判断校正是否成功，如果判断出校正失败，则对第二数据串执行相同的计算。相反，如果判断校正成功，则通过使用上述的校正子集和误差定位多项式的系数来校正第一数据串的错误。

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