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1. 发明授权

US07432581B2 Semiconductor device, method of manufacture thereof and semiconductor integrated circuit 有权
标题翻译：半导体装置及其制造方法以及半导体集成电路
公开(公告)号：US07432581B2
公开(公告)日：2008-10-07
申请号：US11336874
申请日：2006-01-23
申请人： Toshiki Kanamoto , Masumi Yoshida , Tetsuya Watanabe , Takashi Ippoushi
发明人： Toshiki Kanamoto , Masumi Yoshida , Tetsuya Watanabe , Takashi Ippoushi
IPC分类号： H01L29/93
CPC分类号： H01L21/76281 , H01L21/761 , H01L21/84 , H01L27/0207 , H01L27/11807 , H01L27/1203
摘要： An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.
摘要翻译：在与用作PMOS晶体管的漏极区域的P型杂质区域在Y方向上接触的隔离区域中采用FTI结构。首先，用作体区的第二和第三N型杂质层分别经由第四，第五和第六N型杂质层连接到高电位线，并且还经由第七N型杂质层连接。第四至第六N型杂质层设置在SOI衬底的绝缘层和PTI区域中的元件隔离绝缘膜之间。

2. 发明申请

US20060170052A1 Semiconductor device, method of manufacture thereof and semiconductor integrated circuit 有权
标题翻译：半导体装置及其制造方法以及半导体集成电路
公开(公告)号：US20060170052A1
公开(公告)日：2006-08-03
申请号：US11336874
申请日：2006-01-23
申请人： Toshiki Kanamoto , Masumi Yoshida , Tetsuya Watanabe , Takashi Ippoushi
发明人： Toshiki Kanamoto , Masumi Yoshida , Tetsuya Watanabe , Takashi Ippoushi
IPC分类号： H01L27/12
CPC分类号： H01L21/76281 , H01L21/761 , H01L21/84 , H01L27/0207 , H01L27/11807 , H01L27/1203
摘要： An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.
摘要翻译：在与用作PMOS晶体管的漏极区域的P型杂质区域在Y方向上接触的隔离区域中采用FTI结构。首先，用作体区的第二和第三N型杂质层分别经由第四，第五和第六N型杂质层连接到高电位线，并且还经由第七N型杂质层连接。第四至第六N型杂质层设置在SOI衬底的绝缘层和PTI区域中的元件隔离绝缘膜之间。

3. 发明申请

US20050007120A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050007120A1
公开(公告)日：2005-01-13
申请号：US10777068
申请日：2004-02-13
申请人： Kyoji Yamashita , Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto
发明人： Kyoji Yamashita , Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04 , G01R31/08
CPC分类号： G01R31/2884 , G01R31/2853
摘要： PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.
摘要翻译： PMISFET和NMISFET放置在电容测量电路中。每个互连通过相应的PMISFET通过充电电压供应部分连接到电源焊盘，并通过相应的NMISFET通过电流采样部分连接到电流监测焊盘。可以通过将电流表的探头与电流监测板接触来测量电流。

4. 发明授权

US07230435B2 Capacitance measurement circuit 失效
标题翻译：电容测量电路
公开(公告)号：US07230435B2
公开(公告)日：2007-06-12
申请号：US10760449
申请日：2004-01-21
申请人： Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto , Kyoji Yamashita
发明人： Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto , Kyoji Yamashita
IPC分类号： G01R27/26 , G01R27/02
CPC分类号： G01R27/2605
摘要： A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N1) is electrically connected to a terminal (P2) between the drains of PMOS and NMOS transistors (MP2, MN2). As a target capacitance forming part, a coupling capacitance (Cc) is formed between the node (N1) and a node (N2). The node (N2) is connected to a pad (58) through the terminal (P2) and an NMOS transistor (MN3), and a node (N3) is connected to a terminal (P3) between the drains of PMOS and NMOS transistors (MP1, MN1). A reference capacitance (Cref) is formed at the node (N3) as a dummy capacitance. Currents (Ir, It) supplied from a power source to the nodes (N3, N1) are measured with current meters (61, 62), respectively and a current (Im) induced from the node (N2) and flowing to a ground level is measured with a current meter (63).
摘要翻译： CBCM电路能够单独测量测量目标电容的每个分量。节点（N 1）电连接到PMOS和NMOS晶体管（MP 2，MN 2）的漏极之间的端子（P 2）。作为目标电容形成部，在节点（N 1）和节点（N 2）之间形成耦合电容（C SUB）。节点（N 2）经由端子（P 2）和NMOS晶体管（MN 3）连接到焊盘（58），并且节点（N 3）连接到端子（N 3）之间的端子（P 3） PMOS和NMOS晶体管（MP 1，MN 1）。在节点（N 3）处形成参考电容（C SUB）作为虚拟电容。分别用电流计（61,62）从电源向节点（N 3，N 1）提供的电流（I，R，I，T）使用电流计（63）测量从节点（N 2）感应并流到地平面的电流（I SUB）。

5. 发明授权

US06982555B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06982555B2
公开(公告)日：2006-01-03
申请号：US10777068
申请日：2004-02-13
申请人： Kyoji Yamashita , Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto
发明人： Kyoji Yamashita , Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto
IPC分类号： G01R31/08 , G01R31/28
CPC分类号： G01R31/2884 , G01R31/2853
摘要： PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.
摘要翻译： PMISFET和NMISFET放置在电容测量电路中。每个互连通过相应的PMISFET通过充电电压供应部分连接到电源焊盘，并通过相应的NMISFET通过电流采样部分连接到电流监测焊盘。可以通过将电流表的探头与电流监测板接触来测量电流。

6. 发明授权

US07979817B2 Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing 有权
标题翻译：网表制作装置，通过分层处理产生具有互连寄生元件的网络列表
公开(公告)号：US07979817B2
公开(公告)日：2011-07-12
申请号：US12213623
申请日：2008-06-23
申请人： Toshiki Kanamoto , Mitsutoshi Shirota , Michiko Uchimura
发明人： Toshiki Kanamoto , Mitsutoshi Shirota , Michiko Uchimura
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information.
摘要翻译：存储单元信息产生单元获取存储单元的物理终端坐标，物理终端名称和逻辑终端名称以及布局数据，并基于它们进行操作，以指定在存储单元的互连上寄生的寄生元件，并且产生存储单元信息，包括物理终端名称和表示物理特性以及存储器单元的内部元件与寄生元件的连接关系。存储单元阵列信息生成单元获取确定存储单元的物理终端的连接关系的连接信息，基于该连接信息将节点名称分配给存储单元的物理终端，并生成表示全部的节点名称的存储单元阵列信息记忆细胞。存储单元阵列网列表产生单元产生由存储单元信息和存储单元阵列信息形成的存储单元阵列的净列表。

7. 发明授权

US06728943B2 Semiconductor circuit extraction apparatus and method 有权
标题翻译：半导体电路提取装置及方法
公开(公告)号：US06728943B2
公开(公告)日：2004-04-27
申请号：US09848209
申请日：2001-05-04
申请人： Toshiki Kanamoto
发明人： Toshiki Kanamoto
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , H01L21/768 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit extraction apparatus: detects the uppermost wiring layer of a cell; carries out virtual wiring conductor routing on all tracks of a cell-top wiring layer directly overlying the uppermost wiring layer of the cell; extracts parasitic capacitances of all the wiring conductors including those virtually routed; and calculates the delay time of placement/routing data in accordance with the extracted parasitic capacitances to provide highly accurate delay information library data.
摘要翻译：半导体电路提取装置：检测电池的最上层布线层; 在单元顶部布线层的所有轨道上执行虚拟布线导体，直接覆盖在单元的最上布线层上; 提取包括实际路由的所有布线导体的寄生电容; 并根据提取的寄生电容计算放置/路由数据的延迟时间，以提供高精度的延迟信息库数据。

8. 发明授权

US06504186B2 Semiconductor device having a library of standard cells and method of designing the same 失效
标题翻译：具有标准单元库的半导体器件及其设计方法
公开(公告)号：US06504186B2
公开(公告)日：2003-01-07
申请号：US09090379
申请日：1998-06-04
申请人： Toshiki Kanamoto , Yoshihide Ajioka , Yukihiko Shimazu , Hideyuki Hamada
发明人： Toshiki Kanamoto , Yoshihide Ajioka , Yukihiko Shimazu , Hideyuki Hamada
IPC分类号： H01L2710
CPC分类号： H01L27/11803
摘要： In a semiconductor device provided with a plurality of standard cells each comprising an input terminal and MOS transistors, a diffused region having a substantially negligibly small resistance is formed in a semiconductor substrate, and the input terminal of the standard cell and gates of the MOS transistors are connected through the diffused region. Also, a diffused region is formed under the input terminal in the substrate, and the input terminal is connected to the diffused region. In a modification, another standard cell is formed by forming a diffused region and a metal layer connected to the diffused region on the substrate, and the another standard cell is connected to the input terminal.
摘要翻译：在设置有包括输入端子和MOS晶体管的多个标准单元的半导体器件中，在半导体衬底中形成具有基本可忽略的小电阻的扩散区域，并且标准单元的输入端子和MOS晶体管的栅极通过扩散区连接。此外，在基板的输入端子的下方形成扩散区域，输入端子与扩散区域连接。在变形例中，通过形成扩散区域和连接到基板上的扩散区域的金属层来形成另一个标准单元，另一个标准单元连接到输入端子。

9. 发明申请

US20080270967A1 Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing 有权
公开(公告)号：US20080270967A1
公开(公告)日：2008-10-30
申请号：US12213623
申请日：2008-06-23
申请人： Toshiki Kanamoto , Mitsutoshi Shirota , Michiko Uchimura
发明人： Toshiki Kanamoto , Mitsutoshi Shirota , Michiko Uchimura
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information.

10. 发明授权

US07398506B2 Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing 失效
标题翻译：网表制作装置，通过分层处理产生具有互连寄生元件的网络列表
公开(公告)号：US07398506B2
公开(公告)日：2008-07-08
申请号：US11358101
申请日：2006-02-22
申请人： Toshiki Kanamoto , Mitsutoshi Shirota , Michiko Uchimura
发明人： Toshiki Kanamoto , Mitsutoshi Shirota , Michiko Uchimura
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information.
摘要翻译：存储单元信息产生单元获取存储单元的物理终端坐标，物理终端名称和逻辑终端名称以及布局数据，并基于它们进行操作，以指定在存储单元的互连上寄生的寄生元件，并且产生存储单元信息，包括物理终端名称和表示物理特性以及存储器单元的内部元件与寄生元件的连接关系。存储单元阵列信息生成单元获取确定存储单元的物理终端的连接关系的连接信息，基于该连接信息将节点名称分配给存储单元的物理终端，并生成表示全部的节点名称的存储单元阵列信息记忆细胞。存储单元阵列网列表产生单元产生由存储单元信息和存储单元阵列信息形成的存储单元阵列的净列表。

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