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1. 发明授权

US5331584A Discrete cosine transformation processor 失效
标题翻译：离散余弦变换处理器
公开(公告)号：US5331584A
公开(公告)日：1994-07-19
申请号：US997326
申请日：1992-12-28
申请人： Toshiaki Kitsuki , Akira Sawada
发明人： Toshiaki Kitsuki , Akira Sawada
IPC分类号： H03M7/30 , G06F17/14 , G06T9/00 , H04N1/41 , H04N19/42 , H04N19/436 , H04N19/60 , H04N19/625 , G06F7/38
CPC分类号： G06F17/147
摘要： A discrete cosine transformation processor subjects a plurality of input data to addition or subtraction at an adder/subtracter with two combinations according to the control signal every clock pulse so as to output a plurality of combination data. The combination data are assigned to eight groups according to certain combinations and each of them is input to one of eight selection circuits. The selection circuit selects one data from the combination input data according to the control signal and outputs the selected data every clock pulse. A multiplier receives the data selected by the selection circuit and multiplies it by a predetermined coefficient every clock pulse. Further, a second adder/subtracter subjects the output data from the multiplier to addition or subtraction in different combinations according to the control signal to determine cosine transformation coefficient to inverse cosine transformation coefficients.
摘要翻译：离散余弦变换处理器根据每个时钟脉冲根据控制信号，以加法器/减法器对多个输入数据进行加法或减法运算，以输出多个组合数据。根据某些组合将组合数据分配给8组，并将它们中的每一个输入到八个选择电路之一。选择电路根据控制信号从组合输入数据中选择一个数据，并且每个时钟脉冲输出所选择的数据。乘法器接收由选择电路选择的数据，并将每个时钟脉冲乘以预定系数。此外，第二加法器/减法器根据控制信号使来自乘法器的输出数据以不同的组合进行加法或减法，以确定余弦变换系数到逆余弦变换系数。

2. 发明授权

US5754234A Moving picture decoding system 失效
标题翻译：运动图像解码系统
公开(公告)号：US5754234A
公开(公告)日：1998-05-19
申请号：US874575
申请日：1997-06-13
申请人： Toshiaki Kitsuki , Akira Sawada
发明人： Toshiaki Kitsuki , Akira Sawada
IPC分类号： H03M7/30 , G06T9/00 , H04N5/907 , H04N11/04 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/50 , H04N19/503 , H04N19/577 , H04N19/593 , H04N19/61 , H04N19/625 , H04N19/85 , H04N19/91 , H04N7/32
CPC分类号： H04N11/044 , G06T9/007 , H04N19/423 , H04N19/523 , H04N19/61 , H04N5/907
摘要： An adder restores an image data by adding an output of a reverse DCT portion and an output of a predicted value calculating portion to output to a macro-block buffer. Data temporarily stored in the macro-block buffer is written in a predicting dynamic memory per a unit of data of one word consisted of 2.times.2 blocks of luminance component (Y), 1.times.2 blocks of Cr component and 1.times.2 blocks of Cb components, via a memory data bus. A prediction reference block of the preceding frame stored in the predicting dynamic memory is output to a reference block buffer via the memory data bus. A restored image data of the preceding frame in the predicting dynamic memory is output to a line buffer via the memory data bus.
摘要翻译：加法器通过将逆DCT部分的输出和预测值计算部分的输出相加来恢复图像数据，以输出到宏块缓冲器。临时存储在宏块缓冲器中的数据被写入预测动态存储器中，每个单位的数据单位由亮度分量（Y）的2×2块，Cr分量的1×2块和Cb分量的1×2块组成。数据总线。存储在预测动态存储器中的前一帧的预测参考块通过存储器数据总线输出到参考块缓冲器。预测动态存储器中的前一帧的恢复图像数据经由存储器数据总线输出到行缓冲器。

3. 发明授权

US5828785A Method of reducing the number of access times to a reference frame memory in image compression 失效
标题翻译：在图像压缩中减少参考帧存储器的访问次数的方法
公开(公告)号：US5828785A
公开(公告)日：1998-10-27
申请号：US518224
申请日：1995-08-23
申请人： Toshiaki Kitsuki
发明人： Toshiaki Kitsuki
IPC分类号： H04N11/04 , G06T7/20 , H04N5/14 , H04N7/26 , H04N7/32 , G06K9/36 , H04N7/12
CPC分类号： H04N5/145 , G06T7/2013 , H04N19/433 , H04N19/51 , G06T2207/10016
摘要： A search window of data blocks of a reference (viz., previous) frame is established in a search window memory for preparation for estimating displacement of a current data block of a current picture frame within the search window. The search window memory has memory capacity of two times that of the search window. The current picture frame is divided, in horizontal and vertical directions, into a plurality of data blocks which are sequentially written in a current block memory along each of horizontal lines according to a predetermined order of horizontal lines. A reference frame memory is accessed for writing data blocks in the search window memory for completing a search window for a current data block for preparing a part of a search window for a data block located on a horizontal line next to said given horizontal line when the current data block belongs to one of a predetermined number of last data blocks on said given horizontal line. On the other hand, the reference frame memory is accessed for writing data blocks in the search window memory for completing a search window for the current data block when the current data is located on the given horizontal line and outside of the predetermined number of last data blocks.
摘要翻译：在搜索窗口存储器中建立参考（即，先前）帧的数据块的搜索窗口，以准备估计搜索窗口内的当前图像帧的当前数据块的位移。搜索窗口存储器的存储容量是搜索窗口的两倍。当前图像帧在水平和垂直方向被划分为多个数据块，它们根据水平行的预定顺序沿着每个水平行被顺序写入当前块存储器。访问用于在搜索窗口存储器中写入数据块的参考帧存储器，用于完成当前数据块的搜索窗口，用于为位于所述给定水平行旁边的水平线上的数据块的搜索窗口的一部分进行准备当前数据块属于所述给定水平线上的预定数量的最后数据块中的一个。另一方面，当在当前数据位于给定水平线上并且在预定数量的最后数据之外时，参考帧存储器被访问用于在搜索窗口存储器中写入数据块以完成当前数据块的搜索窗口块。

4. 发明授权

US5371546A LSI encoding device with pixel data blocking and vertical decimating circuits 失效
标题翻译：具有像素数据阻塞和垂直抽取电路的LSI编码装置
公开(公告)号：US5371546A
公开(公告)日：1994-12-06
申请号：US237
申请日：1993-01-04
申请人： Toshiaki Kitsuki
发明人： Toshiaki Kitsuki
IPC分类号： H04N7/12 , G06T3/40 , G06T9/00 , H04N11/04 , H04N19/42 , H04N19/423 , H04N19/59 , H04N19/85 , H04N11/02
CPC分类号： H04N11/042 , H04N19/186 , H04N19/59
摘要： An LSI device for encoding an image includes a dot sequential access unit for sequentially storing in an external storage image data arranged in a dot sequential manner, a block data output device for outputting block data from the storage, the block data including the pixel data of a predetermined number of lines and a predetermined number of columns, and a vertical decimating unit for conducting a vertical decimating operation for the block data. The LSI device employs only one memory to achieve the decimating operation and the blocking operation. As a result, the number of pins of the device and the size thereof can be decreased.
摘要翻译：用于对图像进行编码的LSI装置包括用于顺序地存储在以点顺序方式布置的外部存储图像数据中的点顺序存取单元，用于从存储器输出块数据的块数据输出装置，包括预定数量的行和预定数量的列，以及垂直抽取单元，用于对块数据进行垂直抽取操作。 LSI设备仅使用一个存储器来实现抽取操作和阻塞操作。结果，可以减少装置的引脚数及其尺寸。

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