会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Non-volatile semiconductor memory device
    • 非易失性半导体存储器件
    • US06807097B2
    • 2004-10-19
    • US10661571
    • 2003-09-15
    • Yoshinori TakanoTadayuki TauraToru Tanzawa
    • Yoshinori TakanoTadayuki TauraToru Tanzawa
    • G11C1604
    • G11C16/3472G11C11/5621G11C11/5642G11C16/28G11C16/3436G11C16/3481G11C2211/5621G11C2211/5634
    • A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.
    • 非挥发性半导体存储器件包括:每个具有带控制栅极的晶体管结构的电可重写非易失性数据存储单元的阵列; 参考电流源电路,被配置为生成适于在普通读取操作期间使用的第一参考电流和用于在写入和擦除事件之一中的数据状态验证的验证读取操作期间使用的第二参考电流; 读出放大器,被配置为将普通读取操作期间所选择的所选存储单元的读取电流与验证读取操作分别与第一和第二参考电流进行比较,从而执行数据检测; 以及驱动器,被配置为向在普通读取操作和验证读取操作期间当前选择的所选择的存储器单元的控制栅极提供相同的电压。
    • 5. 发明授权
    • Nonvolatile semiconductor memory device with first and second read modes
    • 具有第一和第二读取模式的非易失性半导体存储器件
    • US06842377B2
    • 2005-01-11
    • US10412646
    • 2003-04-11
    • Yoshinori TakanoYasuhiko HondaToru TanzawaMasao Kuriyama
    • Yoshinori TakanoYasuhiko HondaToru TanzawaMasao Kuriyama
    • G11C16/02G11C7/10G11C7/22G11C16/06G11C16/26G11C16/28
    • G11C7/22G11C7/1021G11C16/26G11C16/28G11C2207/2281
    • A nonvolatile semiconductor memory device with a plurality of read modes switchably built therein is provided. This nonvolatile semiconductor memory device is the one that has a memory cell array in which electrically rewritable nonvolatile memory cells are laid out and a read circuit which performs data readout of the memory cell array. The nonvolatile semiconductor memory device has a first read mode and a second read mode. The first read mode is for reading data by means of parallel data transfer of the same bit number when sending data from the memory cell array through the read circuit up to more than one external terminal. The second read mode is for performing parallel data transfer of a greater bit number than that of the first read mode when sending data from the memory cell array to the read circuit while performing data transfer of a smaller bit number than the bit number when sending data from the read circuit up to the external terminal.
    • 提供了一种具有可切换地构建的多个读取模式的非易失性半导体存储器件。 这种非易失性半导体存储器件是具有其中布置有电可重写非易失性存储单元的存储单元阵列,以及执行存储单元阵列的数据读出的读电路。 非易失性半导体存储器件具有第一读取模式和第二读取模式。 第一读取模式是通过从存储单元阵列通过读取电路向多于一个的外部端子发送数据时,通过相同位数的并行数据传输来读取数据。 第二读取模式用于在将数据从存储器单元阵列发送到读取电路时执行比第一读取模式更大位数的并行数据传输,同时在发送数据时执行比位数更小位数的数据传输 从读取电路到外部端子。
    • 7. 发明授权
    • Fast data readout semiconductor storage apparatus
    • 快速数据读出半导体存储装置
    • US06826068B1
    • 2004-11-30
    • US10654463
    • 2003-09-03
    • Hitoshi ShigaYoshinori TakanoToru TanzawaShigeru Atsumi
    • Hitoshi ShigaYoshinori TakanoToru TanzawaShigeru Atsumi
    • G11C506
    • G11C7/1021G11C8/10
    • A semiconductor integrated circuit device includes first to fourth bit lines and a redundant bit line, first to fourth column gate transistors and a redundant column gate transistor coupled to each of the first to fourth bit lines and the redundant bit lines, first to fourth column select lines and a redundant column select line coupled to each of the first to fourth column gate transistors and the redundant column gate transistor. The second column select line passes through the first bit line. The third column select line passes through the first and second bit lines. The fourth column select line passes through the first, second and third bit lines. The redundant column select line passes through the first, second, third and fourth bit lines.
    • 半导体集成电路器件包括第一至第四位线和冗余位线,第一至第四列栅极晶体管和耦合到第一至第四位线和冗余位线中的每一个的冗余列栅极晶体管,第一至第四列选择 线路以及耦合到第一至第四列栅极晶体管和冗余列栅极晶体管中的每一个的冗余列选择线。 第二列选择线通过第一位线。 第三列选择线通过第一和第二位线。 第四列选择线通过第一,第二和第三位线。 冗余列选择线通过第一,第二,第三和第四位线。
    • 8. 发明授权
    • Nonvolatile semiconductor memory device with initialization circuit and control method thereof
    • 具有初始化电路的非易失性半导体存储器件及其控制方法
    • US06535427B1
    • 2003-03-18
    • US09707983
    • 2000-11-08
    • Yoshinori TakanoToru TanzawaTadayuki Taura
    • Yoshinori TakanoToru TanzawaTadayuki Taura
    • G11C1626
    • G11C7/12G11C7/20G11C16/24G11C16/26
    • A memory cell is connected to a cell-based bit line. The cell-based bit line is connected to a bit line via a Y decoder. The bit line is connected to a sense bit line via a separation circuit. This sense bit line is connected to a sense line via a bias circuit. An amplifier circuit amplifies a signal voltage on the sense line together with a reference voltage for sensing data. The sense line is connected with a sense line initialization circuit for setting the sense line to a specified voltage. The bit line is connected with a bit line initialization circuit for setting the bit line to a specified voltage. Both the sense line initialization circuit and the bit line initialization circuit are activated in a given period before the amplifier circuit operates to sense data. Thus, the sense line and the bit line are set to specified voltages.
    • 存储单元连接到基于单元的位线。 基于单元的位线通过Y解码器连接到位线。 位线通过分离电路连接到感测位线。 该感测位线通过偏置电路连接到感测线。 放大器电路将感测线上的信号电压与用于感测数据的参考电压一起放大。 感测线与感测线初始化电路连接,用于将感测线设置为指定电压。 位线与位线初始化电路连接,用于将位线设置为指定电压。 感测线初始化电路和位线初始化电路在放大器电路操作以感测数据之前的给定时间段内被激活。 因此,感测线和位线被设定为规定的电压。
    • 10. 发明授权
    • Constant voltage generation circuit and semiconductor memory device
    • 恒压发生电路和半导体存储器件
    • US06734719B2
    • 2004-05-11
    • US10238773
    • 2002-09-11
    • Toru TanzawaYoshinori Takano
    • Toru TanzawaYoshinori Takano
    • G05F110
    • G11C5/147
    • A constant voltage generating circuit comprising following elements is shown: a first constant current generation circuit including a first transistor and a second transistor, configured to generate a first voltage and a first current as determined by an operating point to be determined depending on a difference in threshold voltage between the first and second transistors; a second constant current generation circuit configured to generate a second current proportional to said first current; and a voltage generation circuit including a third transistor having its gate and drain connected together, configured to generate a second voltage when letting said second current flow in said third transistor.
    • 示出包括以下元件的恒压产生电路:第一恒流产生电路,包括第一晶体管和第二晶体管,其被配置为产生由操作点确定的第一电压和第一电流,以根据第 所述第一和第二晶体管之间的阈值电压;被配置为产生与所述第一电流成比例的第二电流的第二恒定电流产生电路; 以及包括其栅极和漏极连接在一起的第三晶体管的电压产生电路,被配置为当使所述第二电流流过所述第三晶体管时产生第二电压。