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1. 发明授权

US4945506A High speed digital signal processor capable of achieving realtime operation 失效
标题翻译：能实现实时操作的高速数字信号处理器
公开(公告)号：US4945506A
公开(公告)日：1990-07-31
申请号：US324830
申请日：1989-03-17
申请人： Toru Baji , Hirotsugu Kojima , Nario Sumi , Yoshimune Hagiwara , Shinya Ohba
发明人： Toru Baji , Hirotsugu Kojima , Nario Sumi , Yoshimune Hagiwara , Shinya Ohba
IPC分类号： G06F17/10 , G06F17/16
CPC分类号： G06F17/16
摘要： A digital signal processor for computing a vector product between a column vector input signal including a plurality of data items (x0, x1, x2, . . . , x7) and a matrix including a predetermined number of coefficient data items so as to produce a column vector output signal including a plurality of data items (y0, y1, y2, . . . , y7). In a first cycle, the leading data x0 of the column vector input signal is stored in a first store unit (Rin), whereas during this period of time, in a second cycle shorter in time than the first cycle, the data items (c0, c1, c2, . . . , c7) in the row direction constituting a first portion of the matrix are sequentially read out such that both data items are multiplied, thereby storing the multiplication results in an accumulator. A similar data processing is repeatedly executed so as to obtain, based on the outputs from the accumulator, a column vector output signal constituted by the plurality of data items (y0, y1, y2, . . . , y7).
摘要翻译：一种数字信号处理器，用于在包括多个数据项（x0，x1，x2，...，x7）的列向量输入信号和包括预定数量的系数数据项的矩阵之间计算矢量积，以便产生列向量输出信号包括多个数据项（y0，y1，y2，...，y7）。在第一周期中，列向量输入信号的前导数据x0存储在第一存储单元（Rin）中，而在该时间段内，在比第一周期更短的第二周期中，数据项（c0 顺序地读取构成矩阵的第一部分的行方向的c1，c1，c2，...，c7），使得两个数据项被相乘，从而将乘法结果存储在累加器中。重复执行类似的数据处理，以便基于来自累加器的输出，获得由多个数据项（y0，y1，y2，...，y7）构成的列向量输出信号。

2. 发明授权

US06185595B2 Discrete cosine transformation operation circuit 失效
标题翻译：离散余弦变换运算电路
公开(公告)号：US06185595B2
公开(公告)日：2001-02-06
申请号：US08952653
申请日：1998-03-10
申请人： Toyokazu Hori , Nario Sumi , Masaru Hase
发明人： Toyokazu Hori , Nario Sumi , Masaru Hase
IPC分类号： G06F1714
CPC分类号： G06F17/147
摘要： One multiplier 13 operated at a normalized frequency 4 is provided to multiply the elements of DCT transformation coefficients and the elements of input data, and the multiplication results are added by a cumulative adder 15 to determine cumulative addition results corresponding to the sum (x0+x7) and the difference (x0−x7) of a pair of elements (x0, x7) of data to be outputted from a one-dimensional DCT operation circuit 1. The paired cumulative addition results are added and subtracted by an adder 17 and a subtracter 18, respectively, to determine the elements (x0, x7). The operations are performed specific times the number of which is one half of the number of elements of a column of the matrix of the input data to determine the elements of a column of the matrix of the output data and are performed specific times the number of which is equal to the number of elements of a row of the matrix or the input data to determine all the elements of the matrix of the output data. As a result, the scale of the DCT operation circuit is reduced, thereby reducing the power consumption.
摘要翻译：提供以归一化频率4操作的一个乘法器13，用于将DCT变换系数的元素和输入数据的元素相乘，乘法结果由累积加法器15相加，以确定对应于和（x0 + x7）的累积加法结果）和要从一维DCT运算电路1输出的数据的一对元素（x0，x7）的差（x0-x7）。成对的累积相加结果被加法器17和减法器 18，分别确定元素（x0，x7）。执行操作的特定次数，其数量是输入数据的矩阵的列的元素数量的一半，以确定输出数据的矩阵的列的元素，并且被执行特定次数其等于矩阵的行的元素的数量或输入数据，以确定输出数据的矩阵的所有元素。结果，降低了DCT运算电路的规模，从而降低了功耗。

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