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1. 发明申请

US20120303907A1 Dynamically Maintaining Coherency Within Live Ranges of Direct Buffers 失效
标题翻译：在直接缓冲区的实际范围内动态维护一致性
公开(公告)号：US20120303907A1
公开(公告)日：2012-11-29
申请号：US13584356
申请日：2012-08-13
申请人： Tong Chen , John K. O Brien , Tao Zhang
发明人： Tong Chen , John K. O Brien , Tao Zhang
IPC分类号： G06F12/08
CPC分类号： G06F8/4442
摘要： Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.
摘要翻译：提供了减少数据处理系统中的一致性问题。要编译的源代码被接收和分析以识别包含存储器引用的多个循环中的至少一个循环。确定存储器引用是否是应该由直接缓冲器处理的全局存储器的访问。响应于指示存储器引用是对由直接缓冲器处理的全局存储器的访问，存储器引用被标记用于直接缓冲器转换。然后将直接缓冲区变换应用于存储器引用。

2. 发明授权

US08782381B2 Dynamically rewriting branch instructions in response to cache line eviction 有权
标题翻译：动态地重写分支指令以响应缓存线驱逐
公开(公告)号：US08782381B2
公开(公告)日：2014-07-15
申请号：US13444890
申请日：2012-04-12
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4442 , G06F9/3806 , G06F12/0875 , G06F12/12
摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.
摘要翻译：提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。确定当前高速缓存行是否将从指令高速缓存中逐出。处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

3. 发明授权

US08776034B2 Dynamically maintaining coherency within live ranges of direct buffers 失效
标题翻译：在直接缓冲区的生存范围内动态维护一致性
公开(公告)号：US08776034B2
公开(公告)日：2014-07-08
申请号：US13584356
申请日：2012-08-13
申请人： Tong Chen , John K. O'Brien , Tao Zhang
发明人： Tong Chen , John K. O'Brien , Tao Zhang
IPC分类号： G06F9/45 , G06T13/00 , H04L12/50
CPC分类号： G06F8/4442
摘要： Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.
摘要翻译：提供了减少数据处理系统中的一致性问题。要编译的源代码被接收和分析以识别包含存储器引用的多个循环中的至少一个循环。确定存储器引用是否是应该由直接缓冲器处理的全局存储器的访问。响应于指示存储器引用是对由直接缓冲器处理的全局存储器的访问，存储器引用被标记用于直接缓冲器转换。然后将直接缓冲区变换应用于存储器引用。

4. 发明授权

US08762968B2 Prefetching irregular data references for software controlled caches 失效
标题翻译：预取软件控制缓存的不规则数据引用
公开(公告)号：US08762968B2
公开(公告)日：2014-06-24
申请号：US13534794
申请日：2012-06-27
申请人： Tong Chen , Marc Gonzalez tallada , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , Marc Gonzalez tallada , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4442
摘要： Prefetching irregular memory references into a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain an irregular memory reference. The compiler determines if the irregular memory reference within the at least one loop is a candidate for optimization. Responsive to an indication that the irregular memory reference may be optimized, the compiler determines if the irregular memory reference is valid for prefetching. Responsive to an indication that the irregular memory reference is valid for prefetching, a store statement for an address of the irregular memory reference is inserted into the at least one loop. A runtime library call is inserted into a prefetch runtime library for the irregular memory reference. Data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked.
摘要翻译：提供了将不规则内存引用预取到软件控制的缓存中。编译器分析源代码以识别包含不规则存储器引用的多个循环中的至少一个循环。编译器确定至少一个循环内的不规则存储器引用是否是优化的候选者。响应于可以优化不规则存储器引用的指示，编译器确定不规则存储器引用是否对预取有效。响应于不规则存储器引用对于预取有效的指示，将不规则存储器引用的地址的存储语句插入到至少一个循环中。运行时库调用插入到不规则内存引用的预取运行时库中。当调用运行时库调用时，与不规则内存引用相关联的数据将被预取到软件控制的缓存中。

5. 发明授权

US08627051B2 Dynamically rewriting branch instructions to directly target an instruction cache location 有权
标题翻译：动态地重写分支指令直接指向指令高速缓存位置
公开(公告)号：US08627051B2
公开(公告)日：2014-01-07
申请号：US13442919
申请日：2012-04-10
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F9/3806 , G06F12/0875
摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.
摘要翻译：提供了用于在代码的一部分中动态地重写分支指令的机制。这些机制在代码的一部分中执行分支指令。这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，这些机制将代码部分的执行重定向到指令高速缓存运行时系统。

6. 发明授权

US08285670B2 Dynamically maintaining coherency within live ranges of direct buffers 失效
标题翻译：在直接缓冲区的生存范围内动态维护一致性
公开(公告)号：US08285670B2
公开(公告)日：2012-10-09
申请号：US12177507
申请日：2008-07-22
申请人： Tong Chen , John K. O'Brien , Tao Zhang
发明人： Tong Chen , John K. O'Brien , Tao Zhang
IPC分类号： G06F7/00
CPC分类号： G06F8/4442
摘要： Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.
摘要翻译：提供了减少数据处理系统中的一致性问题。要编译的源代码被接收和分析以识别包含存储器引用的多个循环中的至少一个循环。确定存储器引用是否是应该由直接缓冲器处理的全局存储器的访问。响应于指示存储器引用是对由直接缓冲器处理的全局存储器的访问，存储器引用被标记用于直接缓冲器转换。然后将直接缓冲区变换应用于存储器引用。

7. 发明授权

US08281295B2 Computer analysis and runtime coherency checking 失效
标题翻译：计算机分析和运行时一致性检查
公开(公告)号：US08281295B2
公开(公告)日：2012-10-02
申请号：US12125982
申请日：2008-05-23
申请人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
发明人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/433
摘要： Compiler analysis and runtime coherency checking for reducing coherency problems is provided. Source code is analyzed to identify at least one of a plurality of loops that contains a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by at least one of a software controlled cache or a direct buffer. A determination is made as to whether there is a data dependence between the memory reference and at least one reference from at least one of other direct buffers or other software controlled caches in response to an indication that the memory reference is an access to the global memory that should be handled by either the software controlled cache or the direct buffer. A direct buffer transformation is applied to the memory reference in response to a negative indication of the data dependence.
摘要翻译：提供了编译器分析和运行时相关性检查，以减少相关性问题。分析源代码以识别包含存储器引用的多个循环中的至少一个。确定存储器引用是否是对由软件控制的高速缓存或直接缓冲器中的至少一个来处理的全局存储器的访问。确定响应于存储器引用是对全局存储器的访问的指示，确定存储器引用与来自其他直接缓冲器或其他软件控制的高速缓存中的至少一个的至少一个引用之间是否存在数据依赖性应由软件控制的缓存或直接缓冲区来处理。响应于数据依赖性的负指示，将直接缓冲器变换应用于存储器引用。

8. 发明申请

US20110321021A1 Arranging Binary Code Based on Call Graph Partitioning 有权
标题翻译：基于调用图划分二进制代码
公开(公告)号：US20110321021A1
公开(公告)日：2011-12-29
申请号：US12823244
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.
摘要翻译：提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。这些机制产生一部分代码的调用图。调用图中的节点和边被加权以生成加权调用图。然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码调用图被组合到基于分区的各个高速缓存行。然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

9. 发明申请

US20110321002A1 Rewriting Branch Instructions Using Branch Stubs 有权
标题翻译：使用分支存根重写分支指令
公开(公告)号：US20110321002A1
公开(公告)日：2011-12-29
申请号：US12823204
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K.P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/4436 , G06F8/433 , G06F8/4442
摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.
摘要翻译：提供了用于在一部分代码中重写分支指令的机制。该机制接收一部分具有原始分支指令的源代码。机制为原始分支指令生成分支存根。分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预。

10. 发明申请

US20080229291A1 Compiler Implemented Software Cache Apparatus and Method in which Non-Aliased Explicitly Fetched Data are Excluded 有权
标题翻译：编译器实现的软件缓存设备和方法，其中排除非别名显式提取的数据
公开(公告)号：US20080229291A1
公开(公告)日：2008-09-18
申请号：US12128194
申请日：2008-05-28
申请人： Tong Chen , John Kevin Patrick O'Brien , Kathryn O'Brien , Byoungro So , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , John Kevin Patrick O'Brien , Kathryn O'Brien , Byoungro So , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiler implemented software cache apparatus and method in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.
摘要翻译：提供了一种编译器实现的软件缓存装置和方法，其中排除了非别名显式提取的数据。利用说明性实施例的机制，编译器使用前向数据流分析来证明在缓存的数据和显式提取的数据之间没有别名。在缓存数据中没有别名的显式获取的数据将从软件高速缓存中排除。在缓存数据中具有别名的明确获取的数据被允许存储在软件高速缓存中。以这种方式，没有运行时开销来维护两个数据副本的正确性。此外，必须防止驱逐的软件缓存的行数减少。这导致在高速缓存未命中处理期间驱逐高速缓存行时缓存未命中处理程序所需的计算周期量的减少。

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