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1. 发明授权

US4991083A Method and system for extending address space for vector processing 失效
标题翻译：用于扩展矢量处理的地址空间的方法和系统
公开(公告)号：US4991083A
公开(公告)日：1991-02-05
申请号：US228300
申请日：1988-08-04
申请人： Tomoo Aoyama , Shun Kawabe
发明人： Tomoo Aoyama , Shun Kawabe
IPC分类号： G06F12/08 , G06F12/10 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8084 , G06F12/10
摘要： A method and apparatus for extending an address space for a vector processor including a vector processing unit and a scalar processing unit. A main storage and an extended storage are also disclosed. An address translator is provided for each requestor within the vector processing unit. Each address translator includes registers for storing main storage addresses and extended storage addresses for the address translation, a register for storing information such as an invalid bit regarding an address space present on the main storage, a register for storing information such as a protection bit representative of an address translation enabled area, and registers for storing a reference bit and a write bit representative of the main storage reference status. The scalar processing unit includes an access controller for allowing a write/pad operation relative to the respective registers in the address translator. The vector processing unit includes a first logic circuit for temporarily suspending a main storage reference request sent from the requestor to an area not present on the main storage, a second logic circuit for releasing the suspension, and a third logic circuit for informing the scalar processing unit of the suspension of the main storage reference request.
摘要翻译：一种用于扩展用于包括向量处理单元和标量处理单元的向量处理器的地址空间的方法和装置。还公开了主存储和扩展存储。为向量处理单元内的每个请求者提供地址转换器。每个地址转换器包括用于存储用于地址转换的主存储地址和扩展存储地址的寄存器，用于存储关于存在于主存储器上的地址空间的无效位的信息的寄存器，用于存储诸如保护位代表的地址转换使能区域，以及用于存储参考位和用于表示主存储器参考状态的写入位的寄存器。标量处理单元包括访问控制器，用于允许相对于地址翻译器中的相应寄存器的写/写操作。矢量处理单元包括：第一逻辑电路，用于将从请求者发送的主存储参考请求临时挂起到主存储器上不存在的区域;第二逻辑电路，用于释放暂停;以及第三逻辑电路，用于通知标量处理单位暂停主存储参考请求。

2. 发明授权

US4849882A Vector processing system for processing plural vector instruction streams 失效
标题翻译：用于处理多个向量指令流的向量处理系统
公开(公告)号：US4849882A
公开(公告)日：1989-07-18
申请号：US87603
申请日：1987-08-20
申请人： Tomoo Aoyama , Shun Kawabe
发明人： Tomoo Aoyama , Shun Kawabe
IPC分类号： G06F17/16 , G06F15/78
CPC分类号： G06F15/8084
摘要： A vector processor has a plurality of vector processing units each of which is connected to main storage via a plurality of memory port logic units. Each of the vector processing units has a resource management circuit, thereby managing its resources and the plurality of memory port logic units as resources and reporting information of the memory port logic unit determined to be used to other vector processing units. The plurality of memory port logic units are thus shared by the plurality of vector processing units.
摘要翻译：矢量处理器具有多个矢量处理单元，每个矢量处理单元经由多个存储器端口逻辑单元连接到主存储器。每个矢量处理单元具有资源管理电路，从而管理其资源和多个存储器端口逻辑单元作为确定为用于其他矢量处理单元的存储器端口逻辑单元的资源和报告信息。因此，多个存储器端口逻辑单元由多个向量处理单元共享。

3. 发明授权

US4943912A Parallel processor system having control processor and array control apparatus for selectively activating different processors 失效
标题翻译：具有用于选择性地激活不同处理器的控制处理器和阵列控制装置的并行处理器系统
公开(公告)号：US4943912A
公开(公告)日：1990-07-24
申请号：US106864
申请日：1987-10-13
申请人： Tomoo Aoyama , Hiroshi Murayama
发明人： Tomoo Aoyama , Hiroshi Murayama
IPC分类号： G06F15/80
CPC分类号： G06F15/8015
摘要： A parallel processor system comprises a main storage, a processor array control apparatus, a control processor which requests the processor array control apparatus to execute the processing in accordance with a procedure start instruction, and a plurality of processor elements each containing a local memory. In response to a designation from the control processor, the processor array control apparatus transfers the program from the main storage to the local memories in all of the processor elements before they are driven. The processor array control apparatus then controls the conditions of the processor elements and drives those processor elements which are capable of processing the procedure in accordance with the procedure start instruction from the control processor.
摘要翻译：并行处理器系统包括主存储器，处理器阵列控制装置，控制处理器，其请求处理器阵列控制装置根据过程开始指令执行处理;以及多个处理器元件，每个处理器元件包含本地存储器。响应于来自控制处理器的指定，处理器阵列控制装置在被驱动之前将程序从主存储器传送到所有处理器元件中的本地存储器。然后，处理器阵列控制装置控制处理器元件的状态，并驱动能够根据来自控制处理器的过程开始指令来处理该过程的那些处理器元件。

4. 发明授权

US5007005A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US5007005A
公开(公告)日：1991-04-09
申请号：US329556
申请日：1989-03-28
申请人： Yasuhiko Hatakeyama , Tomoo Aoyama
发明人： Yasuhiko Hatakeyama , Tomoo Aoyama
IPC分类号： G06T13/00 , G06T13/80 , G09G5/36 , G09G5/39 , G09G5/399
CPC分类号： G09G5/363 , G09G5/399
摘要： A data processing system capable of implementing at high speeds animating image generation processing and animating image display processing in synchronization with each other, thereby generating and displaying an animating image in a real time. The data processing system uses a given memory area of a storage unit as a screen buffer memory for storing an animating image data for each screen and is provided with an image processor for writing an animating image data for each screen in a screen buffer memory, an image display processor for reading the animating image data for from the screen buffer memory and for generating a display screen graphic signal to be supplied to a display unit and a hardware register circuit having a screen read-out control register corresponding to the animating image data for each screen of the screen buffer memory. The hardware register circuit updates data of the screen read-out control register in synchronization with each of a write operation of an animating image data from the image processor and a read operation of the animating image data to the image display processor. A delivery and a receipt of the data of the animating image data for each screen is carried out at high speeds between the image processor and the image display processor through the screen buffer memory storing the animating image data therefor by a control of the hardware register circuit.
摘要翻译：一种数据处理系统，其能够高速实现图像生成处理和动画化图像显示处理，从而以实时的方式生成和显示动画图像。数据处理系统使用存储单元的给定存储区作为用于存储每个屏幕的动画图像数据的屏幕缓冲存储器，并且设置有用于将每个屏幕的动画图像数据写入屏幕缓冲存储器的图像处理器，图像显示处理器，用于从屏幕缓冲存储器读取动画图像数据，并产生要提供给显示单元的显示屏图形信号;以及具有与该动画图像数据对应的屏幕读出控制寄存器的硬件寄存器电路，屏幕的每个屏幕缓冲存储器。硬件寄存器电路与来自图像处理器的动画图像数据的写入操作以及动画图像数据的读取操作与图像显示处理器的读取操作同步地更新屏幕读出控制寄存器的数据。在图像处理器和图像显示处理器之间通过屏幕缓冲存储器以高速度传送和接收每个屏幕的动画图像数据，通过硬件寄存器电路的控制来存储其动画图像数据。

5. 发明授权

US4757444A Vector processor capable of performing iterative processing 失效
标题翻译：能够执行迭代处理的向量处理器
公开(公告)号：US4757444A
公开(公告)日：1988-07-12
申请号：US685134
申请日：1984-12-21
申请人： Tomoo Aoyama , Yuuji Aoki , Hiroshi Murayama
发明人： Tomoo Aoyama , Yuuji Aoki , Hiroshi Murayama
IPC分类号： G06F9/38 , G06F15/78 , G06F17/16 , G06F15/347
CPC分类号： G06F15/8076
摘要： There is provided a vector processor based on a pipeline control method in which a cyclic operation is divided into a plurality of stages and processed. This processor comprises a vector register controller for dividing an operating process into a plurality of fundamental process units and controlling these units, and a phase generator for allowing the vector register controller to time-sharingly make the vector processor operative. This vector processor reads out data from vector registers in which vector elements are stored, operates this data and writes the result of operation into the vector register. With this vector processor, a cyclic operation can be processed in parallel at a high speed without causing a remarkable increase in hardware.
摘要翻译：提供了一种基于流水线控制方法的向量处理器，其中循环操作被划分为多个级并被处理。该处理器包括用于将操作过程分成多个基本处理单元并控制这些单元的向量寄存器控制器，以及用于允许向量寄存器控制器分时地使向量处理器可操作的相位发生器。该向量处理器从存储向量元素的向量寄存器中读出数据，操作该数据并将操作结果写入向量寄存器。使用该向量处理器，可以高速并行地处理循环操作，而不会导致硬件显着增加。

6. 发明授权

US4964035A Vector processor capable of high-speed access to processing results from scalar processor 失效
标题翻译：矢量处理器能够高速访问标量处理器的处理结果
公开(公告)号：US4964035A
公开(公告)日：1990-10-16
申请号：US178569
申请日：1988-04-07
申请人： Tomoo Aoyama , Hiroshi Murayama
发明人： Tomoo Aoyama , Hiroshi Murayama
IPC分类号： G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8076
摘要： A vector processing system having a main storage, a vector processor, a scalar processor, and an address translation mechanism in each processor in which data is stored in the main processor. The vector processing system includes a common memory in which processing results of vector data can be directly stored from resources such as arithmetic circuits and an operand fetch logic in the vector processor without using the address translation mechanism and from which data can be directly read out by the resources in the scalar processor without using the address translation mechanism, a common memory access control circuit for controlling the conflict among access requests issued from a plurality of resources in the processors and for controlling the access right through an assignment of a block number in a unit of a logical partition of the common memory, and a circuit for controlling, depending on set information held in the control circuit, a decode operation of an instruction specifying operations of the scalar and vector processors.
摘要翻译：在每个处理器中具有主存储器，矢量处理器，标量处理器和地址转换机构的矢量处理系统，其中数据被存储在主处理器中。矢量处理系统包括公共存储器，其中矢量数据的处理结果可以从矢量处理器中的诸如算术电路和操作数取出逻辑的资源直接存储，而不使用地址转换机制，并且可以从哪个数据直接读出数据不使用地址转换机构的标量处理器中的资源，用于控制从处理器中的多个资源发出的访问请求之间的冲突的公共存储器访问控制电路，并且用于通过分配一个块号码来控制访问权限公共存储器的逻辑分区的单元，以及用于根据控制电路中保存的设置信息来控制指定标量和向量处理器的操作的指令的解码操作的电路。

7. 发明授权

US5247695A Vector processor with byte access of memory 失效
标题翻译：具有字节访问存储器的矢量处理器
公开(公告)号：US5247695A
公开(公告)日：1993-09-21
申请号：US545360
申请日：1990-06-27
申请人： Masamori Kashiyama , Tomoo Aoyama
发明人： Masamori Kashiyama , Tomoo Aoyama
IPC分类号： G06F17/16 , G06F15/78
CPC分类号： G06F15/8076
摘要： A vector processor in which input/output of vector data to and from a vector register is effected by a load/store pipeline from a main memory, includes a load pipe for reading data of a plural-byte width from the main memory in one access, a plurality of vector registers for storing data read by the load pipe, each having a plurality of entries of an 8-byte width, mark bit stacks provided one for each of the vector registers and each having at least the same number of entries as those of the vector register, the entries of each mark bit stack storing mark bits for indicating which one of the plural-byte data stored in the entries of the corresponding vector register is valid, and a shifter for sending the valid data to an operation unit in accordance with the mark stored in the mark bit stack.
摘要翻译：向量处理器，其中向量寄存器的矢量数据的输入/输出是通过来自主存储器的加载/存储流水线进行的，包括用于从一个访问中从主存储器读取多字节宽度的数据的加载管道，多个向量寄存器，用于存储由负载管读取的数据，每个向量寄存器具有多个8字节宽度的条目，标记位堆栈为每个向量寄存器提供一个，每个具有至少相同数量的条目，矢量寄存器的条目，每个标记位堆栈的条目存储用于指示存储在相应向量寄存器的条目中的多字节数据中的哪一个有效的标记位，以及用于将有效数据发送到操作单元的移位器按照存储在标记位堆栈中的标记。

8. 发明授权

US4974145A Processor system including a paging processor for controlling paging between a main storage and an extended storage 失效
标题翻译：处理器系统包括用于控制主存储器和扩展存储器之间的寻呼的寻呼处理器
公开(公告)号：US4974145A
公开(公告)日：1990-11-27
申请号：US277949
申请日：1988-11-30
申请人： Tomoo Aoyama , Hiroshi Murayama
发明人： Tomoo Aoyama , Hiroshi Murayama
IPC分类号： G06F17/16 , G06F12/10
CPC分类号： G06F12/10
摘要： A vector processor having a scalar procesing unit, a vector processing unit, a main storage unit, an extended storage unit, a storage control unit, and a paging processor unit, in which the storage control unit address translation for an access request from the vector processing unit to the main storage unit and includes a circuit for storing a kind of an access request issued for each storage location of the main storage the paging processor unit includes a circuit operative in response to issuance of an access request for data in a logical address space not existing in the main storage unit for interrupting a vector access request related thereto from the vector processing unit, a circuit for releasing the interruption according to an instruction, a circuit for loading the main storage unit with requested data of a logical address space existing in the extended storage unit, and a circuit for detecting an area of the main storage having a lower access frequency so as to move data from the area into the extended storage unit. A microprogram is used to execute programming of an algorithm to achieve a data transfer between the main storage unit and the extended storage unit.
摘要翻译：一种具有标量处理单元，向量处理单元，主存储单元，扩展存储单元，存储控制单元和寻呼处理器单元的向量处理器，其中存储控制单元对来自向量的访问请求进行地址转换处理单元连接到主存储单元，并且包括用于存储针对主存储器的每个存储位置发出的访问请求的类型的电路，寻呼处理器单元包括响应于在逻辑地址中发送数据的访问请求而工作的电路主存储单元中不存在用于从矢量处理单元中断与其有关的向量存取请求的空间，用于根据指令释放中断的电路，用于以存在逻辑地址空间的请求数据加载主存储单元的电路在扩展存储单元中，以及用于检测具有较低访问频率的主存储器的区域以便移动数据的电路 m进入扩展存储单元的区域。微程序用于执行算法的编程，以实现主存储单元和扩展存储单元之间的数据传输。

9. 发明授权

US4780811A Vector processing apparatus providing vector and scalar processor synchronization 失效
标题翻译：矢量处理设备提供向量和标量处理器同步
公开(公告)号：US4780811A
公开(公告)日：1988-10-25
申请号：US881403
申请日：1986-07-02
申请人： Tomoo Aoyama , Hiroshi Murayama
发明人： Tomoo Aoyama , Hiroshi Murayama
IPC分类号： G06F17/16 , G06F9/32 , G06F9/38 , G06F15/78 , G06F15/347
CPC分类号： G06F9/30094 , G06F15/8053 , G06F9/30036 , G06F9/30087 , G06F9/3834 , G06F9/3877
摘要： A vector processing apparatus includes a scalar processor for executing scalar instructions and a vector processor for executing vector instructions. The vector processing apparatus has status code registers (SCR) which can be referred to by both processors through a wait managing circuit. The scalar instructions each have an order assurance instruction to assure an order of execution, and the order assurance instruction and the vector instruction each have a field to designate an SCR. The wait managing circuit renders the execution of the instruction in the scalar processor or the vector processor to wait or enable in accordance with a set status or a reset status of the SCR designated by the instruction field, and sets or resets the SCR designated by the instruction field in response to the completion of execution of the instruction to control synchronization of the execution of instructions in both processors.
摘要翻译：矢量处理装置包括用于执行标量指令的标量处理器和用于执行矢量指令的矢量处理器。矢量处理装置具有可由两个处理器通过等待管理电路参考的状态码寄存器（SCR）。标量指令各自具有确保执行顺序的订单保证指令，并且订单保证指令和向量指令各自具有指定SCR的字段。等待管理电路根据由指令字段指定的SCR的设置状态或复位状态，使标量处理器或向量处理器中的指令执行等待或启用，并且设置或复位由指令字段指定的SCR 指令字段响应于完成执行指令以控制两个处理器中的指令执行的同步。

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