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    • 5. 发明授权
    • Motorcycle lamp for vehicle
    • 汽车摩托车灯
    • US08419244B2
    • 2013-04-16
    • US12840031
    • 2010-07-20
    • Takashi SumadaTomonori HayashiTetsu Horiuchi
    • Takashi SumadaTomonori HayashiTetsu Horiuchi
    • B62J6/00F21V33/00
    • B62J6/005B60Q1/2626B60Q1/2638B60Q1/38F21S41/333
    • A motorcycle includes a seat, side covers covering the periphery of the lower side of the seat and formed in curved shapes to gradually decrease in width toward the rear side of the vehicle. Rear blinkers mounted to left and right portions in the vehicle width direction of the side covers. Each of the rear blinkers includes a base member mounted to the side cover, a bulb and a lens covering the bulb. The left and right rear blinkers are disposed at recesses provided in the side covers. Each of the left and right rear blinkers is mounted to the side cover in such a manner that the lens is substantially entirely exposed from the recess to not overlap with a curved surface of the side cover in plan sectional view as viewed from the upper side of the vehicle, the section containing the optical axis of the bulb.
    • 摩托车包括座椅,覆盖座椅下侧周边的侧盖,并形成为向车辆后侧逐渐减小的弯曲形状。 后侧指示灯安装在侧盖的车宽方向上的左右两部分。 每个后部指示灯包括安装到侧盖的基座构件,灯泡和覆盖灯泡的透镜。 左右后方指示灯设置在设置在侧盖中的凹槽处。 左右后方闪光灯中的每一个以这样的方式安装到侧盖,使得透镜基本上完全从凹部露出,以与从侧盖的弯曲表面重叠的平面截面图中,从俯视图的上侧观察 该车辆,该部分包含灯泡的光轴。
    • 7. 发明申请
    • Semiconductor memory device and method of performing data reduction test
    • 半导体存储器件和执行数据压缩测试的方法
    • US20090268498A1
    • 2009-10-29
    • US12385949
    • 2009-04-24
    • Hideo NomuraTomonori HayashiYuji Sugiyama
    • Hideo NomuraTomonori HayashiYuji Sugiyama
    • G11C5/02G11C5/06G11C7/00H01L23/48
    • G11C7/1045G11C29/1201G11C29/48G11C2207/105H01L25/0657H01L2924/0002H01L2924/30105H01L2924/00
    • A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips.
    • 一种半导体器件,包括封装中包含的多个封装端子,设置在封装上的多个芯片,每个芯片包括存储单元阵列和多个数据输入/输出端子,以及多个数据线控制开关 设置在多个封装端子与多个数据输入/输出端子之间。 每个芯片的多个数据线控制开关以正常模式将每个芯片的数据输入/输出端子连接到多个封装端子中的相应的一个。 多个数据线控制开关在测试模式中将不同芯片中的数据输入/输出端子的不同组连接到封装端子的各组。 数据输入/输出端子的各组属于多个数据输入/输出端子。 封装端子的各组在不同的芯片之间是不同的。
    • 8. 发明授权
    • Semiconductor memory device performing refresh operation and method of testing the same
    • 执行刷新操作的半导体存储器件及其测试方法
    • US08363496B2
    • 2013-01-29
    • US12805238
    • 2010-07-20
    • Tomonori HayashiAkihiko KagamiYuji Sugiyama
    • Tomonori HayashiAkihiko KagamiYuji Sugiyama
    • G11C29/08G11C7/00
    • G11C11/406G11C11/401G11C29/02G11C29/023G11C29/50016
    • A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode.
    • 一种半导体存储器件,包括掩模信息存储电路,其存储指示在存储单元阵列中的多个区域中表示不进行自刷新操作的区域的掩模信息,由自刷新命令激活的掩模确定电路 并且响应于刷新地址和掩模信息之间的匹配的检测而产生匹配信号,以及响应于匹配信号的激活而禁用自刷新操作的刷新操作控制电路。 当测试模式信号被激活时,掩模确定电路也被自动刷新命令激活。 利用这种配置,可以在不实际进入自刷新模式的情况下执行部分阵列自刷新功能的测试。