会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT AND TRANSMITTER APPARATUS HAVING THE SAME
    • 半导体集成电路及其发送装置
    • US20100245663A1
    • 2010-09-30
    • US12376405
    • 2007-07-31
    • Manabu KawabataRyogo YanagisawaToru IwataHirokazu Sugimoto
    • Manabu KawabataRyogo YanagisawaToru IwataHirokazu Sugimoto
    • H04N7/01G06F1/04H04N5/05
    • H03K5/135H03L7/18H03M9/00H04L7/0008
    • A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
    • 一种用于接收并行数据信号和第一时钟信号并输出​​串行数据信号和第二时钟信号的半导体集成电路(10D),其中第一时钟产生电路(15)产生通过将第一时钟 信号X / Y。 第二时钟发生电路(11)具有可变的传输特性,并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分(12)将已被转换的并行数据信号 缩放器(16),与第四时钟信号同步地连接到串行数据信号。 分频器(13)产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器(14)有选择地输出第三和第五时钟​​信号之一作为第二时钟信号。
    • 4. 发明授权
    • Semiconductor integrated circuit and transmitter apparatus having the same
    • 具有相同的半导体集成电路和发射机装置
    • US08004433B2
    • 2011-08-23
    • US12376405
    • 2007-07-31
    • Manabu KawabataRyogo YanagisawaToru IwataHirokazu Sugimoto
    • Manabu KawabataRyogo YanagisawaToru IwataHirokazu Sugimoto
    • H03M9/00
    • H03K5/135H03L7/18H03M9/00H04L7/0008
    • A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
    • 一种用于接收并行数据信号和第一时钟信号并输出​​串行数据信号和第二时钟信号的半导体集成电路(10D),其中第一时钟产生电路(15)产生通过将第一时钟 信号X / Y。 第二时钟发生电路(11)具有可变的传输特性,并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分(12)将已被转换的并行数据信号 缩放器(16),与第四时钟信号同步地连接到串行数据信号。 分频器(13)产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器(14)有选择地输出第三和第五时钟​​信号之一作为第二时钟信号。
    • 5. 发明授权
    • Data receiver device and data transmission/reception system
    • 数据接收设备和数据发送/接收系统
    • US07957498B2
    • 2011-06-07
    • US11995423
    • 2006-07-10
    • Hirokazu SugimotoToru Iwata
    • Hirokazu SugimotoToru Iwata
    • H04L7/00
    • H04L7/0004H04L25/14
    • The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.
    • 数据接收装置包括:位相位同步电路(10),用于执行接收数据信号的相位调整,以设置数据信号与对应的时钟信号之间的预定相位关系; 一旦检测到输入到位相位同步电路(10)的数据信号基于由位相位同步电路(10)相位调整的数据信号而处于稳定状态,则输出检测信号的状态检测电路(20) )和相应的时钟信号。 位相位同步电路(10)在接收到检测信号时初始化数据信号的相位调整。
    • 6. 发明申请
    • DATA RECEIVER DEVICE AND DATA TRANSMISSION/RECEPTION SYSTEM
    • 数据接收设备和数据传输/接收系统
    • US20090086852A1
    • 2009-04-02
    • US11995423
    • 2006-07-10
    • Hirokazu SugimotoToru Iwata
    • Hirokazu SugimotoToru Iwata
    • H04L7/06
    • H04L7/0004H04L25/14
    • The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.
    • 数据接收装置包括:位相位同步电路(10),用于执行接收数据信号的相位调整,以设置数据信号与对应的时钟信号之间的预定相位关系; 一旦检测到输入到位相位同步电路(10)的数据信号基于由位相位同步电路(10)相位调整的数据信号而处于稳定状态,则输出检测信号的状态检测电路(20) )和相应的时钟信号。 位相位同步电路(10)在接收到检测信号时初始化数据信号的相位调整。
    • 8. 发明授权
    • Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system
    • 具有电压检测电路和信号发射和接收系统的半导体集成电路
    • US06944003B2
    • 2005-09-13
    • US10365527
    • 2003-02-13
    • Hirokazu SugimotoTakashi HirataHironori AkamatsuToru IwataSatoshi Takahashi
    • Hirokazu SugimotoTakashi HirataHironori AkamatsuToru IwataSatoshi Takahashi
    • G01R31/28H01L21/66H02H9/04H02H3/24
    • H02H9/046
    • A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.
    • 第一半导体集成电路通过电缆连接到第二半导体集成电路。 在第一半导体集成电路中,当电源电压变得小于设定电压检测电平时,电压检测电路输出电压检测信号来降低电缆的电压并停止工作。 第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。 在这样配置的第一半导体集成电路中,在电源电压小于设定电压检测电平的低电压条件下进行测试时,电压检测电路从外部端子接收控制信号,停止动作 强制。 因此,即使电源电压低于设定电压检测电平,第一半导体集成电路也可以正常工作,直到电源电压达到预定的工作电压下限。 因此,在低电压条件下可以进行运行评估。
    • 9. 发明授权
    • Signal receiving circuit and signal input detection circuit
    • 信号接收电路和信号输入检测电路
    • US07809084B2
    • 2010-10-05
    • US11597794
    • 2005-02-01
    • Hirokazu SugimotoToru Iwata
    • Hirokazu SugimotoToru Iwata
    • H03K9/00
    • G11B20/10009G09G5/006G09G5/12G11B20/10222G11B20/10425G11B20/14G11B2020/10592G11B2220/2562H04N5/775H04N5/781
    • In a signal receiving circuit there are provided N input detection circuits 2a to 2n for receiving clock signals S1-c to SN-c included in N channels of signals S1 to SN. Each of the input detection circuits 2a to 2n detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. The selection circuit 3 selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit 4, the serial/parallel conversion circuit 5, etc., which are shared by N channels.
    • 在信号接收电路中,提供有N个输入检测电路2a至2n,用于接收信号S1至SN的N个信道中包括的时钟信号S1-c至SN-c。 每个输入检测电路2a至2n检测相应信道的输入信号的转变,并进一步确认在转换检测之后正在接收相应信道的信号,从而检测相应信道的信号的输入。 选择电路3选择并输出检测到输入的信道的信号中的时钟信号和数据信号。 所选择的输出信号通过由N个信道共享的相位同步电路4,串行/并行转换电路5等中的每一个依次进行输入处理。