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    • 1. 发明授权
    • Semiconductor memory device with redundant circuit
    • 具有冗余电路的半导体存储器件
    • US06310806B1
    • 2001-10-30
    • US09716322
    • 2000-11-21
    • Tomoki HigashiHiroaki Nakano
    • Tomoki HigashiHiroaki Nakano
    • G11C700
    • G11C29/84
    • A redundant memory circuit stores a defective row address. A switch circuit connects a spare row decoder with the wire for transmitting a row address signal according to the defective row address stored in the redundant memory circuit when the power supply is turned on. A row decoder deactivating circuit, when the power supply is turned on, deactivates the part of the row decoder corresponding to the defective row address according to the defective row address stored in the redundant memory circuit. As a result, when the row address buffer outputs the row address signal corresponding to the defective row address, the spare row decoder decodes the row address signal, thereby selecting a spare word line immediately.
    • 冗余存储器电路存储有缺陷的行地址。 当电源接通时,开关电路根据存储在冗余存储器电路中的有缺陷的行地址,将备用行解码器与用于发送行地址信号的布线相连接。 行解码器去激活电路,当电源接通时,根据存储在冗余存储器电路中的有缺陷的行地址,去激活对应于有缺陷行地址的行解码器的部分。 结果,当行地址缓冲器输出与缺陷行地址对应的行地址信号时,备用行解码器解码行地址信号,从而立即选择备用字线。
    • 10. 发明授权
    • Semiconductor device in which capacitance of a MOS capacitor is complemented with the capacitance of a wiring capacitor
    • MOS电容器的电容与布线电容器的电容互补的半导体器件
    • US07557400B2
    • 2009-07-07
    • US11670605
    • 2007-02-02
    • Osamu WadaHiroaki NakanoHiroshi ItoToshimasa NamekawaAtsushi Nakayama
    • Osamu WadaHiroaki NakanoHiroshi ItoToshimasa NamekawaAtsushi Nakayama
    • H01L27/108H01L29/00
    • H01L29/94H01L23/5223H01L27/0222H01L2924/0002H02M3/073H01L2924/00
    • A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting the drain region and source region of said MOS capacitor.
    • 半导体器件具有其中共同连接漏极区域和MOS结构的源极区域的MOS电容器,并且在共同连接的漏极区域/源极区域和MOS结构的栅极电极之间形成电容; 以及具有通过层间绝缘膜形成在所述MOS电容器上的第一梳状布线的布线电容器连接到所述MOS电容器的栅电极,并且具有突出部分,如梳齿形状突出,第二梳状 通过层间绝缘膜在所述MOS电容器上形成的布线跨越与第一梳状布线的线间绝缘膜布置,连接到漏区和源极区,并且具有突出部分如梳齿突出, 其中,所述第二梳状布线的突出部分与所述第一梳状布线的突出部分交替布置,并且垂直于连接所述MOS电容器的漏极区域和源极区域的沟道方向布置。