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1. 发明授权

US08004014B2 Semiconductor integrated circuit device having metal interconnect regions placed symmetrically with respect to a cell boundary 有权
标题翻译：具有相对于单元边界对称放置的金属互连区域的半导体集成电路器件
公开(公告)号：US08004014B2
公开(公告)日：2011-08-23
申请号：US12542263
申请日：2009-08-17
申请人： Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
发明人： Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
IPC分类号： H01L23/52 , H01L27/04
CPC分类号： H01L27/04 , H01L27/0207 , H01L27/11807
摘要： A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
摘要翻译：提供半导体集成电路的布局结构，可以防止在单元边界附近的金属互连的变窄和断开，而不增加OPC的数据量和处理时间。单元格A和单元格B沿着单元边界彼此相邻。相对于单元边界，金属互连的连接区域到单元边界没有其他互连区域被放置为基本上是轴对称的，而面向单元边界的扩散区域的边相对于单元边界是不对称的。

2. 发明申请

US20080224176A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080224176A1
公开(公告)日：2008-09-18
申请号：US12048837
申请日：2008-03-14
申请人： Kazuyuki Nakanishi , Hidetoshi Nishimura , Tomoaki Ikegami
发明人： Kazuyuki Nakanishi , Hidetoshi Nishimura , Tomoaki Ikegami
IPC分类号： H01L27/10
CPC分类号： H01L27/0203 , H01L27/11807
摘要： A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.
摘要翻译：提供了一种半导体集成电路，其不需要增加OPC的校正时间，并且可靠地抑制由于光学邻近效应引起的栅极长度的不均匀性。在垂直方向上延伸的包括栅极G的多个标准单元（C 1，C 2，C 3，...）在横向方向上排列以形成标准单元行。多个标准单元行在垂直方向上并排设置以形成标准单元组。每个标准单元行在标准单元行的至少一端具有端子标准单元Ce。终端标准单元Ce包括两个或更多个辅助栅极，每个补充栅极是无源晶体管的伪栅极和栅极中的任一个。

3. 发明申请

US20100001404A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100001404A1
公开(公告)日：2010-01-07
申请号：US12542263
申请日：2009-08-17
申请人： Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
发明人： Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
IPC分类号： H01L23/52
CPC分类号： H01L27/04 , H01L27/0207 , H01L27/11807
摘要： A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
摘要翻译：提供半导体集成电路的布局结构，可以防止在单元边界附近的金属互连的变窄和断开，而不增加OPC的数据量和处理时间。单元格A和单元格B沿着单元边界彼此相邻。相对于单元边界，金属互连的连接区域与单元边界不存在其他互连区域被放置为基本上是轴对称的，而面向单元边界的扩散区域的边相对于单元边界是不对称的。

4. 发明申请

US20100308377A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20100308377A1
公开(公告)日：2010-12-09
申请号：US12857926
申请日：2010-08-17
申请人： Kazuyuki NAKANISHI , Hidetoshi Nishimura , Tomoaki Ikegami
发明人： Kazuyuki NAKANISHI , Hidetoshi Nishimura , Tomoaki Ikegami
IPC分类号： H01L27/10
CPC分类号： H01L27/0203 , H01L27/11807
摘要： A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.
摘要翻译：提供了一种半导体集成电路，其不需要增加OPC的校正时间，并且可靠地抑制由于光学邻近效应引起的栅极长度的不均匀性。多个标准单元（C1，C2，C3 ...）各自包括在垂直方向上延伸的栅极G，在横向方向上排列以形成标准单元行。多个标准单元行在垂直方向上并排设置以形成标准单元组。每个标准单元行在标准单元行的至少一端具有端子标准单元Ce。终端标准单元Ce包括两个或更多个辅助栅极，每个补充栅极是无源晶体管的伪栅极和栅极中的任一个。

5. 发明授权

US08368225B2 Semiconductor integrated circuit device having improved interconnect accuracy near cell boundaries 有权
标题翻译：半导体集成电路器件在电池边界附近具有改进的互连精度
公开(公告)号：US08368225B2
公开(公告)日：2013-02-05
申请号：US13113644
申请日：2011-05-23
申请人： Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
发明人： Tomoaki Ikegami , Hidetoshi Nishimura , Kazuyuki Nakanishi
IPC分类号： H01L23/52 , H01L27/04
CPC分类号： H01L27/04 , H01L27/0207 , H01L27/11807
摘要： A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
摘要翻译：提供半导体集成电路的布局结构，可以防止在单元边界附近的金属互连的变窄和断开，而不增加OPC的数据量和处理时间。单元格A和单元格B沿着单元边界彼此相邻。相对于单元边界，金属互连的连接区域与单元边界不存在其他互连区域被放置为基本上是轴对称的，而面向单元边界的扩散区域的边相对于单元边界是不对称的。

6. 发明授权

US07800140B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07800140B2
公开(公告)日：2010-09-21
申请号：US12048837
申请日：2008-03-14
申请人： Kazuyuki Nakanishi , Hidetoshi Nishimura , Tomoaki Ikegami
发明人： Kazuyuki Nakanishi , Hidetoshi Nishimura , Tomoaki Ikegami
IPC分类号： H01L27/10
CPC分类号： H01L27/0203 , H01L27/11807
摘要： A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.
摘要翻译：提供了一种半导体集成电路，其不需要增加OPC的校正时间，并且可靠地抑制由于光学邻近效应引起的栅极长度的不均匀性。多个标准单元（C1，C2，C3 ...）各自包括在垂直方向上延伸的栅极G，在横向方向上排列以形成标准单元行。多个标准单元行在垂直方向上并排设置以形成标准单元组。每个标准单元行在标准单元行的至少一端具有端子标准单元Ce。终端标准单元Ce包括两个或更多个辅助栅极，每个补充栅极是无源晶体管的伪栅极和栅极中的任一个。

7. 发明授权

US08399928B2 Semiconductor device 有权
公开(公告)号：US08399928B2
公开(公告)日：2013-03-19
申请号：US13179214
申请日：2011-07-08
申请人： Tomoaki Ikegami , Kazuyuki Nakanishi , Masaki Tamaru
发明人： Tomoaki Ikegami , Kazuyuki Nakanishi , Masaki Tamaru
IPC分类号： H01L21/00
CPC分类号： H01L27/0207 , H01L27/0248 , H01L27/0255 , H01L27/0629 , H01L27/11898
摘要： A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

8. 发明授权

US09373611B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US09373611B2
公开(公告)日：2016-06-21
申请号：US13427188
申请日：2012-03-22
申请人： Hidetoshi Nishimura , Tomoaki Ikegami
发明人： Hidetoshi Nishimura , Tomoaki Ikegami
IPC分类号： H01L23/52 , H01L27/02 , H01L27/118 , H03K3/356
CPC分类号： H01L27/0207 , H01L27/11807 , H01L2027/11875 , H01L2027/11879 , H01L2027/11881 , H03K3/356121
摘要： First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.
摘要翻译：第一，第二和第三功率布线和多个第一信号布线形成在半导体衬底的上层上，并且至少一个第二信号布线形成在多个第一信号布线的上层上。第一和第二功率布线在单元高度方向上相互分离并在单元宽度方向上延伸。第三功率布线在单元宽度方向上在第一和第二布线之间延伸。多个第一信号布线与第一，第二和第三电力布线分离，并且电连接到多个电路元件中的至少一个。至少一个第二信号布线在单元宽度方向上延伸，并且电连接到多个电路元件和多个第一信号布线中的至少一个。

9. 发明申请

US20070200238A1 Semiconductor integrated circuit apparatus and method of designing the same 审中-公开
标题翻译：半导体集成电路装置及其设计方法
公开(公告)号：US20070200238A1
公开(公告)日：2007-08-30
申请号：US11703626
申请日：2007-02-08
申请人： Tomoaki Ikegami , Hidetoshi Nishimura
发明人： Tomoaki Ikegami , Hidetoshi Nishimura
IPC分类号： H01L23/48
CPC分类号： H01L27/0207 , H01L27/118
摘要： In a semiconductor integrated circuit apparatus formed by a core cell constituting a circuit function and a power wiring cell including a power wiring, a metal of a power wiring unit cell constituting the power wiring cell is formed to take a shape of T, and the power wiring unit cell is disposed adjacently, thereby forming a serial power wiring. The core cell and the power wiring cell are connected to each other through a metal wiring in the core cell in which coordinates in a horizontal direction are preset, and a power signal is thus supplied.
摘要翻译：在由构成电路功能的核心单元形成的半导体集成电路装置和包括电力布线的电力布线单元构成的构成电力布线单元的电力布线单元的金属形成为T的形状，接线单元相邻地配置，由此形成串联电力配线。核心单元和电力线路单元通过在水平方向的坐标预置的核心单元中的金属布线彼此连接，从而提供电力信号。

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