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1. 发明申请

US20090290283A1 Scalable Integrated Circuit High Density Capacitors 有权
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US20090290283A1
公开(公告)日：2009-11-26
申请号：US12511350
申请日：2009-07-29
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

2. 发明授权

US07259956B2 Scalable integrated circuit high density capacitors 有权
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US07259956B2
公开(公告)日：2007-08-21
申请号：US11013789
申请日：2004-12-17
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

3. 发明授权

US08570707B2 Scalable integrated circuit high density capacitors 有权
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US08570707B2
公开(公告)日：2013-10-29
申请号：US13162257
申请日：2011-06-16
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Rangnathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Rangnathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

4. 发明申请

US20120018843A1 Scalable Integrated Circuit High Density Capacitors 有权
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US20120018843A1
公开(公告)日：2012-01-26
申请号：US13162257
申请日：2011-06-16
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Rangnathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Rangnathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

5. 发明授权

US07646253B2 Frequency-locked clock generator 有权
标题翻译：频率锁定时钟发生器
公开(公告)号：US07646253B2
公开(公告)日：2010-01-12
申请号：US11436570
申请日：2006-05-19
申请人： Tom W. Kwan , Ning Li
发明人： Tom W. Kwan , Ning Li
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , H03L7/02
摘要： A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.
摘要翻译：锁频时钟发生器包括压控振荡器（VCO），频率 - 电流转换器，参考电流源和增益级。 VCO产生一个输出信号。频率到电流转换器产生与输出信号的频率成比例的转换器电流。参考电流源产生参考电流。增益级基于转换器电流和参考电流之间的差产生控制信号。控制信号被施加到VCO以调整输出信号的频率。反馈迫使VCO产生输出时钟信号，使得其产生的相应电流（即，转换器电流）等于参考电流。当锁定时，输出信号的频率由锁频时钟发生器的时间常数（或等效时间常数）决定。

6. 发明授权

US07978456B2 Scalable integrated circuit high density capacitors 有权
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US07978456B2
公开(公告)日：2011-07-12
申请号：US12511350
申请日：2009-07-29
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

7. 发明授权

US07656643B2 Scalable integrated circuit high density capacitors 有权
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US07656643B2
公开(公告)日：2010-02-02
申请号：US11878696
申请日：2007-07-26
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或用于形成电容器的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

8. 发明申请

US20090283858A1 Scalable Integrated Circuit High Density Capacitors 失效
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US20090283858A1
公开(公告)日：2009-11-19
申请号：US12511398
申请日：2009-07-29
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganthan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganthan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01L27/06
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或用于形成电容器的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

9. 发明授权

US08000083B2 Scalable integrated circuit high density capacitors 失效
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US08000083B2
公开(公告)日：2011-08-16
申请号：US12511398
申请日：2009-07-29
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01G4/06
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或用于形成电容器的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

10. 发明授权

US07477047B2 Register with default control and built-in level shifter 有权
标题翻译：注册默认控制和内置电平转换器
公开(公告)号：US07477047B2
公开(公告)日：2009-01-13
申请号：US11284199
申请日：2005-11-21
申请人： Ning Li , Tom W. Kwan
发明人： Ning Li , Tom W. Kwan
IPC分类号： G05F1/40
CPC分类号： H02M3/157 , Y10S323/901
摘要： Embodiment of the present invention may provide a switching regulator which may be located within an IC. The switching regulator couples to an external power supply, a plurality of configurable control registers, a plurality of default registers, and a multiplexer. The multiplexer is operable to select an input control signal from either the plurality of configurable control registers or the plurality of default control registers as the output control signal to the switching regulator. This default control signal, although not optimal, allows the switching regulator to be configured in a default condition during start up or power down operations and ensures that the switching regulator may provide a stable, although not necessarily optimal, power output to the various components within the IC.
摘要翻译：本发明的实施例可以提供可以位于IC内的开关调节器。开关稳压器耦合到外部电源，多个可配置控制寄存器，多个默认寄存器和多路复用器。多路复用器可操作以从多个可配置控制寄存器或多个默认控制寄存器中选择输入控制信号作为到开关调节器的输出控制信号。这种默认控制信号尽管不是最佳的，但允许开关稳压器在启动或掉电操作期间被配置为默认状态，并且确保开关稳压器可以提供稳定的但不一定最优的功率输出给各种组件 IC。

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