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1. 发明申请

US20050145943A1 Method for fabricating semiconductor devices having silicided electrodes 有权
标题翻译：制造具有硅化物电极的半导体器件的方法
公开(公告)号：US20050145943A1
公开(公告)日：2005-07-07
申请号：US10978786
申请日：2004-10-18
申请人： Tom Schram , Jacob Hooker , Marcus van Dal
发明人： Tom Schram , Jacob Hooker , Marcus van Dal
IPC分类号： H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L31/0392
CPC分类号： H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6659 , H01L29/7833
摘要： The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide. In one embodiment, those parts of the conductors which have different work functions are formed by etching a layer other than the silicon layer, in particular a metal layer, at the location of one of the two semiconductor structures. Furthermore, a further metal layer is applied over the silicon layer and is used to form a further metal silicide at the location of the second transistor. One embodiment of the invention is particularly suitable for use in CMOS technology and results in both PMOS and NMOS transistors with favourable properties.
摘要翻译：本发明涉及一种半导体器件的制造方法，该半导体器件具有包括具有电介质层和第一导体的第一半导体结构的半导体本体，以及具有电介质层和第二导体的第二半导体结构，该第一导体其与介电层邻接，其功函数不同于第二导体的相应部分的功函数。在本发明的一个实施例中，在将介电层施加到半导体本体之后，将金属层施加到所述介电层上，然后在该金属层上沉积硅层并与金属层反应在第一半导体结构的位置处形成金属硅化物。在一个实施例中，通过在两个半导体结构之一的位置处蚀刻除了硅层以外的层，特别是金属层，形成具有不同功函数的导体的这些部分。此外，在硅层上施加另外的金属层，并且用于在第二晶体管的位置形成另外的金属硅化物。本发明的一个实施例特别适用于CMOS技术，并且导致具有良好特性的PMOS和NMOS晶体管。

2. 发明申请

US20070020930A1 Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions 有权
标题翻译：通过降低连接区域的接触电阻的方法制造的半导体器件
公开(公告)号：US20070020930A1
公开(公告)日：2007-01-25
申请号：US11526116
申请日：2006-09-22
申请人： Robert Lander , Marcus van Dal , Jacob Hooker
发明人： Robert Lander , Marcus van Dal , Jacob Hooker
IPC分类号： H01L21/44
CPC分类号： H01L21/28079 , H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L21/28556 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/665
摘要： A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer from a first metal, such that, in the metal cluster layer, metal clusters alternate with sites where there are no metal clusters, the first metal being a non-siliciding metal at predetermined conditions, ii) depositing a metal layer of a second metal on top of the metal cluster layer, the second metal being a siliciding metal and iii) carrying out at least one heat treatment at the predetermined conditions on the second metal layer so as to form metal silicide through reaction of the second metal with the silicon region, wherein atoms of the first metal are displaced in a direction substantially perpendicular to the surface of the substrate.
摘要翻译：公开了一种半导体器件，其通过方法制造，具有半导体结构，其具有在衬底的表面中和/或表面上形成至少一个连接区域的硅区域。在一个实施例中，该方法包括：i）至少在硅区域形成来自第一金属的金属簇层，使得在金属簇层中，金属簇与不存在金属簇的位置交替，第一金属在预定条件下是非硅化金属，ii）在金属簇层的顶部上沉积第二金属的金属层，第二金属是硅化金属，和iii）在预定条件下进行至少一次热处理在第二金属层上，以便通过第二金属与硅区域的反应形成金属硅化物，其中第一金属的原子在基本上垂直于衬底表面的方向上移位。

3. 发明申请

US20060152086A1 Method of manufacturing a semiconductor device and semiconductor device obatined with such a method 审中-公开
公开(公告)号：US20060152086A1
公开(公告)日：2006-07-13
申请号：US10539224
申请日：2003-12-15
申请人： Vincent Venezia , Charles Dachs , Jacob Hooker , Marcus Van Dal
发明人： Vincent Venezia , Charles Dachs , Jacob Hooker , Marcus Van Dal
IPC分类号： H02B1/24
CPC分类号： H01L29/41783 , H01L21/26586 , H01L21/28097 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/1045 , H01L29/4975 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833 , Y10T307/74
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided, at a surface thereof, with a source region (2) and a drain region (3) and with a gate region (4) between the source region (2) and the drain region (3), which gate region comprises a semiconductor region (4A) of a further semiconductor material that is separated from the surface of the semiconductor body (1) by a gate dielectric (5), and with spacers (6) adjacent to the gate region (4), for forming the source and drain regions (2,3), in which method the source region (2) and the drain region (3) are provided with a metal layer (7) which is used to form a compound (8) of the metal and the semiconductor material, and the gate region (4) is provided with a metal layer (7) which is used to form a compound (8) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions (2,3,4) has several drawbacks. A method according to the invention is characterized in that before the spacers (6) are formed, a sacrificial region (4B) of a material that may be selectively etched with respect to the semiconductor region (4A) is deposited on top of the semiconductor region (4A), and after the spacers (6) have been formed, the sacrificial layer (4B) is removed by etching, and after removal of the sacrificial layer (4B), a single metal layer (7) is deposited contacting the source, drain and gate regions (2,3,4). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate (4).

4. 发明申请

US20050112875A1 Method for reducing the contact resistance of the connection regions of a semiconductor device 有权
标题翻译：降低半导体器件的连接区域的接触电阻的方法
公开(公告)号：US20050112875A1
公开(公告)日：2005-05-26
申请号：US10966141
申请日：2004-10-15
申请人： Robert Lander , Marcus van Dal , Jacob Hooker
发明人： Robert Lander , Marcus van Dal , Jacob Hooker
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/786 , H01L21/20 , H01L21/3205 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/28079 , H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/28052 , H01L21/28097 , H01L21/28518 , H01L21/28556 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/665
摘要： One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal cluster layer from a first, non-siliciding metal, followed by the deposition of a metal layer consisting of a second, siliciding metal. A subsequent heat treatment is responsible for forming a metal silicide from the second metal, the atoms of the first metal being displaced in a direction substantially perpendicular to the surface of the substrate. According to one embodiment of the invention, the atoms of the first metal are displaced by the Kirkendall effect to beneath the metal silicide. If an MOST, for example, is being fabricated, this has advantages both at the location of the source and drain region and at the location of the gate electrode.
摘要翻译：本发明的一个实施例涉及一种用于制造具有半导体结构的半导体器件的方法，所述半导体器件具有在衬底的表面中和/或表面上形成至少一个连接区域的硅区域。该方法包括由第一非硅化金属形成金属簇层，随后沉积由第二硅化金属构成的金属层。随后的热处理负责从第二金属形成金属硅化物，第一金属的原子在基本上垂直于衬底的表面的方向上移位。根据本发明的一个实施方案，第一金属的原子由Kirkendall效应位移到金属硅化物的下方。例如，如果制造MOST，则在源极和漏极区域以及栅电极的位置都具有优点。

5. 发明申请

US20070215951A1 SEMICONDUCTOR DEVICES HAVING SILICIDED ELECTRODES 审中-公开
标题翻译：具有硅电极的半导体器件
公开(公告)号：US20070215951A1
公开(公告)日：2007-09-20
申请号：US11750916
申请日：2007-05-18
申请人： Tom Schram , Jacob Hooker , Marcus Henricus van Dal
发明人： Tom Schram , Jacob Hooker , Marcus Henricus van Dal
IPC分类号： H01L29/94
CPC分类号： H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/6659 , H01L29/7833
摘要： The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide. In one embodiment, those parts of the conductors which have different work functions are formed by etching a layer other than the silicon layer, in particular a metal layer, at the location of one of the two semiconductor structures. Furthermore, a further metal layer is applied over the silicon layer and is used to form a further metal silicide at the location of the second transistor. One embodiment of the invention is particularly suitable for use in CMOS technology and results in both PMOS and NMOS transistors with favourable properties.
摘要翻译：本发明涉及一种半导体器件的制造方法，该半导体器件具有包括具有电介质层和第一导体的第一半导体结构的半导体本体，以及具有电介质层和第二导体的第二半导体结构，该第一导体其与介电层邻接，其功函数不同于第二导体的相应部分的功函数。在本发明的一个实施例中，在将介电层施加到半导体本体之后，将金属层施加到所述介电层上，然后在该金属层上沉积硅层并与金属层反应在第一半导体结构的位置处形成金属硅化物。在一个实施例中，通过在两个半导体结构之一的位置处蚀刻除了硅层以外的层，特别是金属层，形成具有不同功函数的导体的这些部分。此外，在硅层上施加另外的金属层，并且用于在第二晶体管的位置形成另外的金属硅化物。本发明的一个实施例特别适用于CMOS技术，并且导致具有良好特性的PMOS和NMOS晶体管。

6. 发明授权

US08932551B2 C-11 cyanide production system 有权
标题翻译： C-11氰化物生产系统
公开(公告)号：US08932551B2
公开(公告)日：2015-01-13
申请号：US13584033
申请日：2012-08-13
申请人： Dohyun Kim , David Alexoff , Sung Won Kim , Jacob Hooker , Richard A. Ferrieri
发明人： Dohyun Kim , David Alexoff , Sung Won Kim , Jacob Hooker , Richard A. Ferrieri
IPC分类号： C01C3/02 , C07B59/00
CPC分类号： B01J8/0285 , B01J8/0278 , B01J8/0492 , B01J8/0496 , B01J2208/00415 , B01J2208/00823 , B01J2208/00893 , B01J2208/024 , C01C3/0212 , C01C3/0216 , C01C3/0229 , C07B59/00
摘要： A method for providing 11C-labeled cyanides from 11C labeled oxides in a target gas stream retrieved from an irradiated high pressure gaseous target containing O2 is provided, wherein 11C labeled oxides are reduced with H2 in the presence of a nickel catalyst under a pressure and a temperature sufficient to form a product stream comprising at least about 95% 11CH4 , the 11CH4 is then combined with an excess of NH3 in a carrier/reaction stream flowing at an accelerated velocity and the combined 11CH4 carrier/reaction stream is then contacted with a platinum (Pt) catalyst particulate supported on a substantially-chemically-nonreactive heat-stable support at a temperature of at least about 900 ° C., whereby a product stream comprising at least about 60%H11CN is provided in less than 10 minutes from retrieval of the 11C labeled oxide.
摘要翻译：提供了一种从含有O 2的被照射的高压气态靶中提取的目标气体流中的11C标记的氧化物提供11C标记的氰化物的方法，其中在镍催化剂存在下，在压力下，用H 2还原11℃标记的氧化物，温度足以形成包含至少约95％11CH4的产物流，然后将11CH4与以加速速度流动的载体/反应物流中的过量NH 3合并，然后将组合的11CH 4载体/反应物流与铂（Pt）催化剂颗粒，其在至少约900℃的温度下负载在基本上化学反应性的热稳定性载体上，由此在不到10分钟内提供包含至少约60％H11CN的产物流， 11C标记的氧化物。

7. 发明申请

US20130045151A1 C-11 Cyanide Production System 有权
标题翻译： C-11氰化物生产系统
公开(公告)号：US20130045151A1
公开(公告)日：2013-02-21
申请号：US13584033
申请日：2012-08-13
申请人： Dohyun Kim , David Alexoff , Sung Won Kim , Jacob Hooker , Richard A. Ferrieri
发明人： Dohyun Kim , David Alexoff , Sung Won Kim , Jacob Hooker , Richard A. Ferrieri
IPC分类号： C01C3/02 , B01D53/02 , C07C1/20 , B01J8/00
CPC分类号： B01J8/0285 , B01J8/0278 , B01J8/0492 , B01J8/0496 , B01J2208/00415 , B01J2208/00823 , B01J2208/00893 , B01J2208/024 , C01C3/0212 , C01C3/0216 , C01C3/0229 , C07B59/00
摘要： A method for providing 11C-labeled cyanides from 11C labeled oxides in a target gas stream retrieved from an irradiated high pressure gaseous target containing O2, wherein 11C labeled oxides are reduced with H2 in the presence of a nickel catalyst under a pressure and a temperature sufficient to form a product stream comprising at least about 95% 11CH4, the 11CH4 is then combined with an excess of NH3 in a carrier/reaction stream flowing at an accelerated velocity and the combined 11CH4 carrier/reaction stream is then contacted with a platinum (Pt) catalyst particulate supported on a substantially-chemically-nonreactive heat-stable support at a temperature of at least about 900° C., whereby a product stream comprising at least about 60% H11CN is provided in less than 10 minutes from retrieval of the 11C labeled oxide.
摘要翻译：在从含有O 2的被照射的高压气态靶中回收的目标气体流中，从11℃标记的氧化物中提供11C标记的氰化物的方法，其中在镍催化剂存在下，在压力和温度足够的情况下，用H 2还原11℃标记的氧化物以形成包含至少约95％11CH4的产物流，然后将11CH4与以加速速度流动的载体/反应物流中的过量NH 3合并，然后将组合的11CH 4载体/反应物流与铂（Pt ）催化剂颗粒在至少约900℃的温度下负载在基本上化学反应性热稳定的载体上，由此在不到10分钟内提供包含至少约60％H11CN的产物流，从11C 标记氧化物。

8. 发明申请

US20090302389A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH DIFFERENT METALLIC GATES 审中-公开
标题翻译：制造具有不同金属门的半导体器件的方法
公开(公告)号：US20090302389A1
公开(公告)日：2009-12-10
申请号：US12066707
申请日：2006-09-11
申请人： Robert Lander , Mark Van Dal , Jacob Hooker
发明人： Robert Lander , Mark Van Dal , Jacob Hooker
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28097 , H01L29/4958 , H01L29/66545 , H01L29/78
摘要： A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor layer (26) is formed over gate dielectric (24) and patterned to be present in a first region (16) not a second region (18). Then, metal (30) is deposited and patterned to be present in the second region not the first. Then, a fully suicided gate process is carried out to result in a fully suicided gate structure in the first region and a gate structure in the second region including the fully suicided gate structure above the deposited metal (30).
摘要翻译：描述了在单个衬底上形成具有不同金属的栅极结构的方法。在栅极电介质（24）上形成薄的半导体层（26），并被图案化以存在于不是第二区域（18）的第一区域（16）中。然后，金属（30）被沉积并图案化以存在于不是第一区域的第二区域中。然后，进行完全自动的栅极处理，以在第一区域中产生完全自述的栅极结构，并且在第二区域中的栅极结构包括沉积金属（30）上方的完全自蚀的栅极结构。

9. 发明申请

US20060134848A1 Method of manufacturing a semiconductor device with mos transistors comprising gate electrodes formed in a packet of metal layers deposited upon one another 有权
标题翻译：制造具有MOS晶体管的半导体器件的方法，包括形成在彼此沉积的金属层的分组中的栅电极
公开(公告)号：US20060134848A1
公开(公告)日：2006-06-22
申请号：US10544413
申请日：2004-01-15
申请人： Robert Lander , Jacob Hooker , Robertus Wolters
发明人： Robert Lander , Jacob Hooker , Robertus Wolters
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/321 , H01L21/28079 , H01L21/28088 , H01L21/823437 , H01L21/82345 , H01L29/4958 , H01L29/4966
摘要： Method of manufacturing a semiconductor device comprising MOS transistors having gate electrodes (15, 16) formed in a number of metal layers (8, 9, 13; 8, 12, 13) deposited upon one another. In this method, active silicon regions (4, 5) provided with a layer of a gate dielectric (7) and field-isolation regions (6) insulating these regions with respect to each other are formed in a silicon body (1). Then, a layer off a first metal (8) is deposited in which locally, at the location of a part of the active regions (4), nitrogen is introduced. On the layer of the first metal, a layer of a second metal (13) is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal (9) which is permeable to nitrogen is deposited on the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric. Substantial changes of the metal work function are possible, and a semiconductor device comprising NMOS and PMOS can be realized.
摘要翻译：一种制造半导体器件的方法，包括：MOS晶体管，其具有形成在彼此沉积的多个金属层（8,9,13; 8,12,13）中的栅电极（15,16）。在这种方法中，在硅体（1）中形成具有栅极电介质层（7）的层和在这些区域彼此绝缘的场隔离区域（6）的有源硅区域（4,5）。然后，沉积第一金属（8）上的层，其中局部地在一部分有源区（4）的位置处引入氮。在第一金属层上沉积第二金属层（13），然后在金属层中蚀刻栅电极。在将氮气引入第一金属层之前，在第一金属层上沉积有氮渗透的第三金属（9）的辅助层。因此，第一金属层可以局部氮化，而不会损坏下面的栅极电介质。可以实现金属功函数的显着变化，并且可以实现包括NMOS和PMOS的半导体器件。

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