专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07225374B2 ABIST-assisted detection of scan chain defects 有权
标题翻译： ABIST辅助检测扫描链缺陷
公开(公告)号：US07225374B2
公开(公告)日：2007-05-29
申请号：US10728348
申请日：2003-12-04
申请人： Todd Michael Burdine , Donato Orazio Forlenza , Orazio Pasquale Forlenza , William James Hurley , Steven Michnowski , James Bernard Webb
发明人： Todd Michael Burdine , Donato Orazio Forlenza , Orazio Pasquale Forlenza , William James Hurley , Steven Michnowski , James Bernard Webb
IPC分类号： G01R31/28
CPC分类号： G01R31/318569
摘要： An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.
摘要翻译：一种装置，程序产品和方法利用在集成电路装置上提供的ABIST电路来帮助识别和定位也在集成电路装置上提供的扫描链中的缺陷。特别地，可以通过将多个图案组应用于耦合到ABIST电路的扫描链来检测扫描链中的缺陷，从而将由多个图案组应用的结果生成的数据收集到扫描链中并且使用所收集的扫描数据来识别扫描链中的有缺陷的锁存器。

2. 发明授权

US07395469B2 Method for implementing deterministic based broken scan chain diagnostics 有权
标题翻译：用于实现基于确定性的断层扫描链诊断的方法
公开(公告)号：US07395469B2
公开(公告)日：2008-07-01
申请号：US10821160
申请日：2004-04-08
申请人： Adrian C. Anderson , Todd Michael Burdine , Donato Orazio Forlenza , Orazio Pasquale Forlenza , William James Hurley , Phong T. Tran
发明人： Adrian C. Anderson , Todd Michael Burdine , Donato Orazio Forlenza , Orazio Pasquale Forlenza , William James Hurley , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G01R31/318569 , G01R31/318583 , G01R31/318591
摘要： A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.
摘要翻译：提供了一种用于实现基于确定性的断层扫描链诊断的方法，装置和计算机程序产品。生成确定性测试模式，并通过应用系统时钟的系统数据端口使用横向插入将其加载到被测设备中的每个扫描链中。然后每个扫描链都被卸载，并且识别出最后一个切换锁存器。测试步骤重复选定次数。然后检查一致的结果。当确定一致的结果时，所识别的最后一个切换锁存器被发送到物理故障分析系统。

3. 发明申请

US20080189583A1 APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING DETERMINISTIC BASED BROKEN SCAN CHAIN DIAGNOSTICS 有权
标题翻译：装置和计算机程序产品，用于实施基于确定的断层扫描链诊断
公开(公告)号：US20080189583A1
公开(公告)日：2008-08-07
申请号：US12101925
申请日：2008-04-11
申请人： Adrian C. Anderson , Todd Michael Burdine , Donato Orazio Forlenza , Orazio Pasquale Forlenza , William James Hurley , Phong T. Tran
发明人： Adrian C. Anderson , Todd Michael Burdine , Donato Orazio Forlenza , Orazio Pasquale Forlenza , William James Hurley , Phong T. Tran
IPC分类号： G01R31/3183 , G06F11/263
CPC分类号： G01R31/318569 , G01R31/318583 , G01R31/318591
摘要： A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.
摘要翻译：提供了一种用于实现基于确定性的断层扫描链诊断的方法，装置和计算机程序产品。生成确定性测试模式，并通过应用系统时钟的系统数据端口使用横向插入将其加载到被测设备中的每个扫描链中。然后每个扫描链都被卸载，并且识别出最后一个切换锁存器。测试步骤重复选定次数。然后检查一致的结果。当确定一致的结果时，所识别的最后一个切换锁存器被发送到物理故障分析系统。

4. 发明授权

US07475308B2 implementing deterministic based broken scan chain diagnostics 有权
标题翻译：实施基于确定性的断层扫描链诊断
公开(公告)号：US07475308B2
公开(公告)日：2009-01-06
申请号：US12101925
申请日：2008-04-11
申请人： Adrian C. Anderson , Todd Michael Burdine , Donato Orazio Forlenza , Orazio Pasquale Forlenza , William James Hurley , Phong T. Tran
发明人： Adrian C. Anderson , Todd Michael Burdine , Donato Orazio Forlenza , Orazio Pasquale Forlenza , William James Hurley , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G01R31/318569 , G01R31/318583 , G01R31/318591
摘要： A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.
摘要翻译：提供了一种用于实现基于确定性的断层扫描链诊断的方法，装置和计算机程序产品。生成确定性测试模式，并通过应用系统时钟的系统数据端口使用横向插入将其加载到被测设备中的每个扫描链中。然后每个扫描链都被卸载，并且识别出最后一个切换锁存器。测试步骤重复选定次数。然后检查一致的结果。当确定一致的结果时，所识别的最后一个切换锁存器被发送到物理故障分析系统。

5. 发明授权

US08086924B2 Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns 有权
标题翻译：使用内置自检LBIST测试模式的逻辑实现过渡扫描链缺陷诊断
公开(公告)号：US08086924B2
公开(公告)日：2011-12-27
申请号：US12250085
申请日：2008-10-13
申请人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Phong T Tran
发明人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Phong T Tran
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/3183 , G01R31/318547
摘要： A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.
摘要翻译：提供了一种方法，设备和计算机程序产品，用于使用结构逻辑内置自检（LBIST）测试模式实现过渡扫描链缺陷的诊断。将LBIST测试模式应用于被测设备，并且具有可变环路控制的多个系统时钟序列应用于通过的操作区域，并且扫描数据被卸载。将LBIST测试模式应用于被测器件，并且将具有可变环路控制的多个系统时钟序列应用于被测器件的故障操作区域，并且扫描数据被卸载。然后比较从通过的操作区域和故障操作区域卸载数据。具有不同结果的识别的锁存器被识别为潜在的AC缺陷锁存器。所识别的潜在AC缺陷锁存器被发送到物理故障分析系统。

6. 发明授权

US08065575B2 Implementing isolation of VLSI scan chain using ABIST test patterns 有权
标题翻译：使用ABIST测试模式实现VLSI扫描链的隔离
公开(公告)号：US08065575B2
公开(公告)日：2011-11-22
申请号：US12250103
申请日：2008-10-13
申请人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Phong T Tran
发明人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Phong T Tran
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于使用结构阵列自检（ABIST）测试模式实现VLSI AC扫描链缺陷的隔离。 ABIST测试图案被应用于被测设备，并且多个ABIST阵列算法被应用在通过的操作区域中并且每个扫描链被卸载。 ABIST测试模式应用于被测设备，并且在被测设备的故障操作区域中应用多个ABIST阵列算法。然后比较从通过的操作区域和故障操作区域卸载数据。具有不同结果的识别的锁存器被识别为潜在的AC缺陷锁存器。所识别的潜在AC缺陷锁存器被发送到物理故障分析系统。

7. 发明申请

US20100095177A1 Implementing Diagnosis of Transitional Scan Chain Defects Using LBIST Test Patterns 有权
标题翻译：使用LBIST测试模式实施过渡扫描链缺陷诊断
公开(公告)号：US20100095177A1
公开(公告)日：2010-04-15
申请号：US12250085
申请日：2008-10-13
申请人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Phong T. Tran
发明人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Phong T. Tran
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G01R31/3183 , G01R31/318547
摘要： A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.
摘要翻译：提供了一种方法，设备和计算机程序产品，用于使用结构逻辑内置自检（LBIST）测试模式实现过渡扫描链缺陷的诊断。将LBIST测试模式应用于被测设备，并且具有可变环路控制的多个系统时钟序列应用于通过的操作区域，并且扫描数据被卸载。将LBIST测试模式应用于被测器件，并且将具有可变环路控制的多个系统时钟序列应用于被测器件的故障操作区域，并且扫描数据被卸载。然后比较从通过的操作区域和故障操作区域卸载数据。具有不同结果的识别的锁存器被识别为潜在的AC缺陷锁存器。所识别的潜在AC缺陷锁存器被发送到物理故障分析系统。

8. 发明申请

US20100095169A1 Implementing Isolation of VLSI Scan Chain Using ABIST Test Patterns 有权
标题翻译：使用ABIST测试模式实现VLSI扫描链的隔离
公开(公告)号：US20100095169A1
公开(公告)日：2010-04-15
申请号：US12250103
申请日：2008-10-13
申请人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Phong T. Tran
发明人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Phong T. Tran
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318536
摘要： A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于使用结构阵列自检（ABIST）测试模式实现VLSI AC扫描链缺陷的隔离。 ABIST测试图案被应用于被测设备，并且多个ABIST阵列算法被应用在通过的操作区域中并且每个扫描链被卸载。 ABIST测试模式应用于被测设备，并且在被测设备的故障操作区域中应用多个ABIST阵列算法。然后比较从通过的操作区域和故障操作区域卸载数据。具有不同结果的识别的锁存器被识别为潜在的AC缺陷锁存器。所识别的潜在AC缺陷锁存器被发送到物理故障分析系统。

9. 发明授权

US07921346B2 Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD) 有权
标题翻译：阵列内置自检（ABIST）设计/诊断设计（DFT / DFD）的验证
公开(公告)号：US07921346B2
公开(公告)日：2011-04-05
申请号：US12262976
申请日：2008-10-31
申请人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Bryan J. Robbins , Phong T. Tran
发明人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Bryan J. Robbins , Phong T. Tran
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G06F11/2236 , G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.
摘要翻译：一种用于测试设计可测性/设计诊断（DFT / DFD）和支持自定义微代码数组的BIST功能的方法，系统和计算机程序产品。在LSSD冲洗和扫描测试完成后，应用ABIST程序来瞄准ABIST阵列的逻辑相关直流（DC）和交流（AC）故障设计可测试性/设计为诊断DFT / DFD功能支持微代码数组。通过应用针对ABIST设计为测试故障的生成的LSSD确定性测试模式来确定DFT功能组合逻辑的LSSD测试，以确定支持微代码阵列的DFT是否正常工作。在阵列周围应用的ABIST DFT电路导致故障时，可能会终止额外的测试。

10. 发明申请

US20100115337A1 VERIFICATION OF ARRAY BUILT-IN SELF-TEST (ABIST) DESIGN-FOR-TEST/DESIGN-FOR-DIAGNOSTICS (DFT/DFD) 有权
标题翻译：校验设计自检（DFT / DFD）设计测试/设计诊断（DFT / DFD）
公开(公告)号：US20100115337A1
公开(公告)日：2010-05-06
申请号：US12262976
申请日：2008-10-31
申请人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Bryan J. Robbins , Phong T. Tran
发明人： Donato Orazio Forlenza , Orazio Pasquale Forlenza , Bryan J. Robbins , Phong T. Tran
IPC分类号： G06F11/07
CPC分类号： G01R31/318544 , G06F11/2236 , G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.
摘要翻译：一种用于测试设计可测性/设计诊断（DFT / DFD）和支持自定义微代码数组的BIST功能的方法，系统和计算机程序产品。在LSSD冲洗和扫描测试完成后，应用ABIST程序来瞄准ABIST阵列的逻辑相关直流（DC）和交流（AC）故障设计可测试性/设计为诊断DFT / DFD功能支持微代码数组。通过应用针对ABIST设计为测试故障的生成的LSSD确定性测试模式来确定DFT功能组合逻辑的LSSD测试，以确定支持微代码阵列的DFT是否正常工作。在阵列周围应用的ABIST DFT电路导致故障时，可能会终止额外的测试。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式