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1. 发明授权

US06822312B2 Interdigitated multilayer capacitor structure for deep sub-micron CMOS 有权
标题翻译：深亚微米CMOS的交叉多层电容器结构
公开(公告)号：US06822312B2
公开(公告)日：2004-11-23
申请号：US09545785
申请日：2000-04-07
申请人： Tirdad Sowlati , Vickram Vathulya
发明人： Tirdad Sowlati , Vickram Vathulya
IPC分类号： H01L2900
CPC分类号： H01L27/0805 , H01L27/0688 , H01L28/40 , H01L28/90
摘要： A capacitor structure having a first level of electrically conductive parallel lines and at least a second level of electrically conductive parallel lines disposed over the lines in the first level, the lines of the first and second levels being arranged in vertical rows. A dielectric layer is disposed between the first and second levels of conductive lines. One or more vias connect the first and second level lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. Electrically opposing nodes form the terminals of the capacitor. The parallel array of vertical capacitor plates are electrically connected to the nodes in an alternating manner so that the plates have alternating electrical polarities.
摘要翻译：一种电容器结构，其具有第一级导电平行线和至少第二级别的导电平行线，其设置在第一级中的线上，第一级和第二级的线被布置成垂直行。电介质层设置在第一和第二层次的导线之间。一个或多个通孔连接每行中的第一和第二电平线，从而形成垂直电容器板的平行阵列。电相对的节点形成电容器的端子。垂直电容器板的平行阵列以交替的方式电连接到节点，使得板具有交替的电极性。

2. 发明授权

US06747307B1 Combined transistor-capacitor structure in deep sub-micron CMOS for power amplifiers 有权
标题翻译：用于功率放大器的深亚微米CMOS组合晶体管 - 电容器结构
公开(公告)号：US06747307B1
公开(公告)日：2004-06-08
申请号：US09542711
申请日：2000-04-04
申请人： Vickram Vathulya , Tirdad Sowlati
发明人： Vickram Vathulya , Tirdad Sowlati
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L23/5223 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A combined transistor and capacitor structure comprising a transistor having alternating source and drain regions formed in a substrate of semiconductor material, and a capacitor formed over the transistor. The capacitor has at least first and second levels of electrically conductive parallel lines arranged in vertical rows, and at least one via connecting the first and second levels of lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. A dielectric material is disposed between the vertical plates of the array. The vertical array of capacitor plates are electrically connected to the alternating source and drain regions of the transistor which form opposing nodes of the capacitor and electrically interdigitate the vertical array of capacitor plates.
摘要翻译：一种组合晶体管和电容器结构，包括在半导体材料的衬底中形成的具有交替的源极和漏极区域的晶体管，以及形成在晶体管上的电容器。电容器至少具有排列成垂直行的第一级和第二级的导电平行线，以及至少一个通孔，其连接每行中的第一和第二级线，由此形成垂直电容器板的平行阵列。介电材料设置在阵列的垂直板之间。电容器板的垂直阵列电连接到形成电容器的相对节点的晶体管的交流源极和漏极区域，并电连接电容器板的垂直阵列。

3. 发明授权

US06570210B1 Multilayer pillar array capacitor structure for deep sub-micron CMOS 有权
标题翻译：用于深亚微米CMOS的多层立柱阵列电容器结构
公开(公告)号：US06570210B1
公开(公告)日：2003-05-27
申请号：US09596443
申请日：2000-06-19
申请人： Tirdad Sowlati , Vickram Vathulya
发明人： Tirdad Sowlati , Vickram Vathulya
IPC分类号： H01L31119
CPC分类号： H01L28/82
摘要： A capacitor structure, especially for use in deep sub-micron CMOS, having an array of electrically conductive pillars which form the plates of the capacitor. Each of the pillars is formed by electrically conductive lines segments from at least two different conductor levels electrically connected by an electrically conductive via. Dielectric material is disposed between the two conductor levels and the pillars of the array. The pillars are electrically connected to opposing nodes in an alternating manner so that the pillars are electrically interdigitated.
摘要翻译：特别是用于深亚微米CMOS的电容器结构具有形成电容器板的导电柱阵列。每个支柱由通过导电通孔电连接的至少两个不同导体层的导电线段形成。电介质材料设置在阵列的两个导体层和支柱之间。支柱以交替的方式电连接到相对的节点，使得支柱是电互扣的。

4. 发明授权

US06410954B1 Multilayered capacitor structure with alternately connected concentric lines for deep sub-micron CMOS 有权
标题翻译：用于深亚微米CMOS的具有交替连接的同心线的多层电容器结构
公开(公告)号：US06410954B1
公开(公告)日：2002-06-25
申请号：US09546125
申请日：2000-04-10
申请人： Tirdad Sowlati , Vickram Vathulya
发明人： Tirdad Sowlati , Vickram Vathulya
IPC分类号： H01L27108
CPC分类号： H01L28/90 , H01L27/0805
摘要： A capacitor structure having a first and at least a second level of electrically conductive concentric lines of an open-loop configuration. The conductive lines of the at least second level overlie the conductive lines of the first level. A dielectric material is disposed between the first and second levels of conductive lines and between the conductive lines in each of the first and second levels. The conductive lines are electrically connected in an alternating manner to terminals of opposing polarity so that capacitance is generated between adjacent lines in each level and in adjacent levels. The capacitor especially useful in deep sub-micron CMOS.
摘要翻译：一种电容器结构，其具有开环构造的第一和至少第二水平的导电同心线。至少第二级的导线覆盖第一级的导线。电介质材料设置在第一级和第二级的导线之间，并且在第一级和第二级中的每一级之间的导线之间。导线以交替的方式电连接到具有相反极性的端子，使得在每个电平和相邻电平中的相邻线之间产生电容。该电容器特别适用于深亚微米CMOS。

5. 发明授权

US06297524B1 Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS 有权
标题翻译：具有用于深亚微米CMOS的同心环形板阵列的多层电容器结构
公开(公告)号：US06297524B1
公开(公告)日：2001-10-02
申请号：US09542712
申请日：2000-04-04
申请人： Vickram Vathulya , Tirdad Sowlati
发明人： Vickram Vathulya , Tirdad Sowlati
IPC分类号： H01G430
CPC分类号： H01L28/82 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure having a first and at least a second conductor level of electrically conductive concentric ring-shaped lines. The conductive lines of the first and at least second levels are arranged in concentric ring-shaped stacks. A dielectric material is disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels. At least one electrically conductive via electrically connects the conductive lines in each stack, thereby forming a concentric array of ring-shaped capacitor plates. The concentric array of capacitor plates are electrically connected in an alternating manner to first and second terminals of opposite polarity so that capacitance is generated between adjacent plates of the array. The capacitor structure is especially useful in deep sub-micron CMOS.
摘要翻译：一种具有导电同心环形线的第一和至少第二导体水平的电容器结构。第一和至少第二级的导线被布置成同心环形的叠层。电介质材料设置在第一和第二导体层之间以及在每一层中的同心导电线之间。至少一个导电通孔电连接每个叠层中的导电线，由此形成环形电容器板的同心阵列。电容器板的同心阵列以交替的方式电连接到具有相反极性的第一和第二端子，使得在阵列的相邻板之间产生电容。电容器结构在深亚微米CMOS中特别有用。

6. 发明授权

US06636119B2 Compact cascode radio frequency CMOS power amplifier 失效
公开(公告)号：US06636119B2
公开(公告)日：2003-10-21
申请号：US09745620
申请日：2000-12-21
申请人： Vickram Vathulya
发明人： Vickram Vathulya
IPC分类号： H03F304
CPC分类号： H03F1/223
摘要： An integrated circuit chip includes a cascode amplifier having a first NMOS transistor with the gate receiving an input signal a source connected to ground through an inductance and a drain connected to the source of a second NMOS transistor. The drain of the second transistor is connected to a supply voltage through another inductance. The gate of the second transistor is connected to a DC bias voltage through a resistor and is connected to a first plate of an on-chip parallel plate capacitor. The other plate of the capacitor is connected to a wirebond pad for connection to a circuit board through a bond wire. The capacitor together with the inductance of the bond wire form a short circuit at the operating voltage of the amplifier.

7. 发明授权

US07126814B2 Space-saver design for personal computer keyboard 失效
公开(公告)号：US07126814B2
公开(公告)日：2006-10-24
申请号：US10740704
申请日：2003-12-19
申请人： Vickram Vathulya
发明人： Vickram Vathulya
IPC分类号： H05K5/00
CPC分类号： A47B21/0314
摘要： A space-saving frame member for use in supporting a keyboard adjacent to a monitor. The frame member has an upper end and a lower end, and means for attaching the upper end of the frame member to the monitor such that the lower end of the frame member extends from a lower side of the monitor to support the keyboard. The frame member may be retractable such that when in an extended position, the user can access the keyboard. When the keyboard is no longer in use, the frame member may be retracted such that the keyboard is stored beneath and behind the monitor.

8. 发明授权

US06725030B2 CMOS radio frequency amplifier with inverter driver 失效
标题翻译： CMOS射频放大器带有变频器驱动器
公开(公告)号：US06725030B2
公开(公告)日：2004-04-20
申请号：US09753107
申请日：2000-12-28
申请人： Vickram Vathulya
发明人： Vickram Vathulya
IPC分类号： H04D116
CPC分类号： H03F3/193 , H03F1/301 , H03F3/345
摘要： A MOSFET amplifier includes a pre-amplifier stage and a power amplifier stage. The pre-amplifier is a CMOS inverter having a signal output that is DC connected to the gate of a MOS control transistor of the power amplifier stage. The CMOS inverter includes an NMOS transistor with a source connected through an inductor to ground and a drain to the source of a PMOS transistor. The drain of the PMOS transistor is connected through another inductor to a supply voltage. The gates of the NMOS and PMOS transistors are connected to both receive an input signal of the amplifier.
摘要翻译： MOSFET放大器包括前置放大器级和功率放大级。前置放大器是具有与功率放大器级的MOS控制晶体管的栅极连接的信号输出的CMOS反相器。 CMOS反相器包括NMOS晶体管，其源极通过电感器连接到地，而漏极连接到PMOS晶体管的源极。 PMOS晶体管的漏极通过另一个电感器连接到电源电压。 NMOS和PMOS晶体管的栅极被连接以接收放大器的输入信号。

9. 发明申请

US20060114050A1 Minimizing i/f noise configuration for zif mixer 审中-公开
标题翻译：最小化zif混频器的i / f噪声配置
公开(公告)号：US20060114050A1
公开(公告)日：2006-06-01
申请号：US10538573
申请日：2003-12-05
申请人： Vickram Vathulya , Luca Lococo
发明人： Vickram Vathulya , Luca Lococo
IPC分类号： G06F7/44
CPC分类号： H03D7/1433 , H03D7/1425 , H03D7/1458 , H03D2200/0033 , H03D2200/0043
摘要： A Gilbert cell (Q3-Q8) of a mixer (11) controls a differential output voltage between a pair of output terminals (OUT1, OUT2) of the mixer (11). A polysilicon resistor (R7) of the mixer (11) applies a differential loading to the differential output voltage. A pair of current sources (Q11, Q12) of the mixer (11) provide biasing currents to the Gilbert cell (Q3-Q8). A pair of resistors (R8, R9) of the mixer (11) impede a flow of DC current through the current sources (Q11, Q12), respectively.
摘要翻译：混合器（11）的吉尔伯特单元（Q 3 -Q 8）控制混频器（11）的一对输出端子（OUT 1，OUT 2）之间的差分输出电压。混合器（11）的多晶硅电阻器（R 7）对差分输出电压施加差分负载。混合器（11）的一对电流源（Q 11，Q 12）向Gilbert单元（Q 3 -Q 8）提供偏置电流。混合器（11）的一对电阻（R 8，R 9）分别阻止通过电流源（Q 11，Q 12）的直流电流。

10. 发明授权

US06747492B2 Power-on reset circuit with current shut-off and semiconductor device including the same 失效
标题翻译：带电流切断的上电复位电路和包括其的半导体器件
公开(公告)号：US06747492B2
公开(公告)日：2004-06-08
申请号：US10174320
申请日：2002-06-18
申请人： Alok Govil , Vickram Vathulya
发明人： Alok Govil , Vickram Vathulya
IPC分类号： H03K1722
CPC分类号： H03K17/223 , H03K2217/0036
摘要： A power-on reset circuit input stage includes a current source charging a capacitor from a first power supply voltage to produce a reset signal, and a current shutoff means for shutting off the current source when the reset signal reaches a desired threshold voltage (i.e., when the capacitor is charged up). Beneficially, the current shutoff means comprises a transistor connected between the current source and a second power supply voltage. Advantageously, the transistor is controlled by a feedback voltage that may be the output signal, or a voltage derived from the output signal by a capacitive divider, for example.
摘要翻译：上电复位电路输入级包括从第一电源电压向电容器充电以产生复位信号的电流源，以及当复位信号达到期望的阈值电压时关闭电流源的电流切断装置（即，当电容充电时）。有利地，当前的关闭装置包括连接在电流源和第二电源电压之间的晶体管。有利地，晶体管由例如可以是输出信号的反馈电压或由电容分压器从输出信号导出的电压来控制。

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