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1. 发明授权

US6156671A Method for improving characteristic of dielectric material 有权
标题翻译：改善介电材料特性的方法
公开(公告)号：US6156671A
公开(公告)日：2000-12-05
申请号：US266177
申请日：1999-03-10
申请人： Ting-Chang Chang , Po-Tsun Liu , Water Lur
发明人： Ting-Chang Chang , Po-Tsun Liu , Water Lur
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/31
CPC分类号： H01L21/02137 , H01L21/02282 , H01L21/0234 , H01L21/3122 , H01L21/31058
摘要： A method for improving a characteristic of a dielectric material. A methylsilsesquioxane having a low dielectric constant is used as a dielectric material. A methylsilsesquioxane film is formed on a substrate. A baking process is performed on the methylsilsesquioxane film, and then a curing process is performed on the methylsilsesquioxane film. Next, a hydrogen plasma treatment is performed on the surface of the methylsilsesquioxane film to prevent the methylsilsesquioxane film from being damaged by oxygen plasma for removing photoresist layer, so that the characteristically low dielectric constant of the methylsilsesquioxane film is maintained.
摘要翻译：一种改善介电材料特性的方法。使用具有低介电常数的甲基倍半硅氧烷作为介电材料。在基板上形成甲基倍半硅氧烷膜。对甲基倍半硅氧烷膜进行烘烤处理，然后对甲基倍半硅氧烷膜进行固化处理。接着，对甲基倍半硅氧烷膜的表面进行氢等离子体处理，以防止甲基倍半硅氧烷膜被除去光致抗蚀剂层的氧等离子体损坏，从而维持甲基硅倍半氧烷薄膜的特性低的介电常数。

2. 发明授权

US07701007B2 Thin film transistor with source and drain separately formed from amorphus silicon region 有权
标题翻译：源极和漏极的薄膜晶体管分别由非晶硅区域形成
公开(公告)号：US07701007B2
公开(公告)日：2010-04-20
申请号：US11393742
申请日：2006-03-31
申请人： Chi-Wen Chen , Ting-Chang Chang , Po-Tsun Liu , Kuo-Yu Huang , Jen-Chien Peng
发明人： Chi-Wen Chen , Ting-Chang Chang , Po-Tsun Liu , Kuo-Yu Huang , Jen-Chien Peng
IPC分类号： H01L27/12
CPC分类号： H01L29/66765 , H01L27/124 , H01L27/1248
摘要： A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.
摘要翻译：薄膜晶体管包括形成在基板上的栅电极; 覆盖栅电极的栅极绝缘层; 设置在栅极绝缘层上和栅电极上方的非晶硅（a-Si）区; 形成在a-Si区上的掺杂a-Si区; 源极和漏极金属区域分别形成在掺杂的a-Si区域和栅电极上方，并与a-Si区域隔离; 形成在所述栅极绝缘层上并覆盖所述源极，漏极和数据线（DL）金属区域的钝化层; 以及形成在钝化层上的导电层。钝化层具有用于分别暴露源极，漏极和DL金属区域的部分表面的第一，第二和第三通孔。第一，第二和第三通孔填充有导电层，使得DL和源极金属区域经由导电层连接。

3. 发明授权

US07022571B2 Quantum structure and forming method of the same 有权
标题翻译：量子结构和形成方法相同
公开(公告)号：US07022571B2
公开(公告)日：2006-04-04
申请号：US10426873
申请日：2003-05-01
申请人： Ting-Chang Chang , Po-Tsun Liu
发明人： Ting-Chang Chang , Po-Tsun Liu
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , B82Y10/00 , H01L21/28194 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/517
摘要： A quantum structure and the forming method based on the difference in characteristic of two matters is provided. The forming method includes several steps. At first, providing a first dielectric layer for forming a second dielectric layer thereon. The second dielectric layer has major elements and impurities contained. Treating the second dielectric layer to drive the impurities to form the quantum structure. For example, oxidizing the major elements to drive the impurities in the first dielectric layer to form the quantum structure in said first dielectric layer because the oxidizing capability of the major elements is stronger than that of the impurities.
摘要翻译：提供了基于两个特征的差异的量子结构和形成方法。成型方法包括几个步骤。首先，提供用于在其上形成第二电介质层的第一电介质层。第二电介质层含有主要元素和杂质。处理第二介质层以驱动杂质以形成量子结构。例如，氧化主要元素以驱动第一电介质层中的杂质以在所述第一介电层中形成量子结构，因为主要元素的氧化能力比杂质的氧化能力更强。

4. 发明授权

US06423652B1 Post-processing treatment of low dielectric constant material 失效
标题翻译：低介电常数材料的后处理处理
公开(公告)号：US06423652B1
公开(公告)日：2002-07-23
申请号：US09420960
申请日：1999-10-19
申请人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
发明人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
IPC分类号： H01L2131
CPC分类号： H01L21/02137 , H01L21/02203 , H01L21/02282 , H01L21/02351 , H01L21/265 , H01L21/3105 , H01L21/3121
摘要： A post-processing treatment of a low dielectric constant material. In the post-processing treatment, a shallow implantation is conducted to form a shallow compact layer over a dielectric film. This shallow compact surface layer acts as a barrier that prevents the absorption of moisture by the dielectric film. The shallow implantation is carried out using boron ions at an energy level of between about 10 and 50 keV and a dosage of between about 1×1015 atm/cm2 and 1×1016 atm/cm2.
摘要翻译：对低介电常数材料进行后处理处理。在后处理处理中，进行浅注入以在电介质膜上形成浅致密层。这种浅的紧密表面层用作防止电介质膜吸收水分的屏障。在约10至50keV的能级和约1×10 15 atm / cm 2和1×10 16 atm / cm 2的剂量之间使用硼离子进行浅注入。

5. 发明授权

US06232198B1 Method for fabricating electrode 失效
标题翻译：电极制造方法
公开(公告)号：US06232198B1
公开(公告)日：2001-05-15
申请号：US09321510
申请日：1999-05-27
申请人： Ting-Chang Chang , Po-Tsun Liu
发明人： Ting-Chang Chang , Po-Tsun Liu
IPC分类号： H01L2120
CPC分类号： H01L28/60 , H01L21/288 , H01L28/55
摘要： A method for fabricating a noble metal electrode of a capacitor. A substrate having a doped region is provided. A dielectric layer is formed to cover the substrate including the doped region with a contact is penetrating through the dielectric layer to couple with the doped region. A barrier layer is formed to cover the dielectric layer and the contact. A polysilicon layer is formed on the barrier layer. The polysilicon layer and TiN barrier layer are etched to form an electrode pattern. The chip is immersed in a solution having noble metal ions and reducing agent for the noble metal ions. In such solution, a displacement reaction takes place to displace the polysilicon layer by a noble metal layer. After the immersion step, the chip is annealed to densify the noble metal layer.
摘要翻译：一种用于制造电容器的贵金属电极的方法。提供具有掺杂区域的衬底。形成介电层以覆盖包括掺杂区域的衬底，其中触点穿过介电层以与掺杂区域耦合。形成阻挡层以覆盖介电层和接触。在阻挡层上形成多晶硅层。蚀刻多晶硅层和TiN阻挡层以形成电极图案。将该芯片浸入具有贵金属离子和贵金属离子还原剂的溶液中。在这种解决方案中，发生置换反应以通过贵金属层移置多晶硅层。在浸渍步骤之后，将芯片退火以使贵金属层致密。

6. 发明授权

US06673661B1 Self-aligned method for forming dual gate thin film transistor (TFT) device 有权
标题翻译：用于形成双栅极薄膜晶体管（TFT）器件的自对准方法
公开(公告)号：US06673661B1
公开(公告)日：2004-01-06
申请号：US10324965
申请日：2002-12-20
申请人： Chi-Wen Liu , Ting-Chang Chang , Po-Tsun Liu , Ying-Lang Wang
发明人： Chi-Wen Liu , Ting-Chang Chang , Po-Tsun Liu , Ying-Lang Wang
IPC分类号： H01L2184
CPC分类号： H01L29/6675 , H01L29/78612 , H01L29/78618 , H01L29/78648 , H01L29/78684
摘要： A method for fabricating a dual gate thin film transistor (TFT) device provides for forming a pair of source/drain layers self-aligned with respect to a first gate electrode and forming a second gate electrode self-aligned with respect to both the pair of source/drain layers and the first gate electrode. Thus, the dual gate TFT device is fabricated with enhanced alignment. In addition, the dual gate TFT device (or a single gate TFT device) may be fabricated with source/drain layers formed of a silicon-germanium alloy material, such as to provide the TFT device with enhanced performance with respect to a kink effect.
摘要翻译：制造双栅极薄膜晶体管（TFT）器件的方法提供了形成相对于第一栅极电极自对准的一对源极/漏极层，并且形成相对于所述一对栅极电极自对准的第二栅电极源极/漏极层和第一栅极电极。因此，双栅极TFT器件被制造成具有增强的对准。此外，双栅极TFT器件（或单栅极TFT器件）可以由硅 - 锗合金材料形成的源极/漏极层制造，以提供相对于扭结效应具有增强性能的TFT器件。

7. 发明授权

US06521547B1 Method of repairing a low dielectric constant material layer 有权
标题翻译：修复低介电常数材料层的方法
公开(公告)号：US06521547B1
公开(公告)日：2003-02-18
申请号：US09682479
申请日：2001-09-07
申请人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
发明人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
IPC分类号： H01L2131
CPC分类号： H01L21/3105 , H01L21/31058 , H01L21/31138 , H01L21/76802
摘要： A method of repairing a low dielectric constant (low k) material layer starts with coating a photoresist layer on the low k material layer on a semiconductor wafer. After transferring a pattern of the photoresist layer to the low k material layer, an oxygen plasma ashing process is performed to remove the photoresist layer. Finally, by contacting the low k material layer with a solution of alkyl silane comprising an alkyl group and halo substituent, Si—OH bonds formed in the low k layer during the oxygen plasma ashing process are removed so as to repair damage to the low k material layer caused by the oxygen plasma ashing process, and to enhance a surface of the low k material layer to a hydrophobic surface to prevent moisture adhering to the surface of the low k material layer.
摘要翻译：修复低介电常数（低k）材料层的方法首先在半导体晶片上的低k材料层上涂覆光致抗蚀剂层。在将光致抗蚀剂层的图案转印到低k材料层之后，进行氧等离子体灰化处理以除去光致抗蚀剂层。最后，通过使低k材料层与包含烷基和卤素取代基的烷基硅烷的溶液接触，除去在氧等离子体灰化过程中在低k层中形成的Si-OH键，以修复对低k 由氧等离子体灰化过程引起的材料层，并且将低k材料层的表面增强到疏水表面以防止水分粘附到低k材料层的表面。

8. 发明申请

US20070052020A1 Thin film transistor and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20070052020A1
公开(公告)日：2007-03-08
申请号：US11393742
申请日：2006-03-31
申请人： Chi-Wen Chen , Ting-Chang Chang , Po-Tsun Liu , Kuo-Yu Huang , Jen-Chien Peng
发明人： Chi-Wen Chen , Ting-Chang Chang , Po-Tsun Liu , Kuo-Yu Huang , Jen-Chien Peng
IPC分类号： H01L27/12
CPC分类号： H01L29/66765 , H01L27/124 , H01L27/1248
摘要： A Thin Film Transistor comprises a gate electrode formed on a substrate; a gate insulation layer covering the gate electrode; an amorphous silicon (a-Si) region disposed on the gate insulation layer and above the gate electrode; a doped a-Si region formed on the a-Si region; the source and drain metal regions separately formed on the doped a-Si region and above the gate electrode, and isolated from the a-Si region; a passivation layer formed on the gate insulation layer and covering the source, drain and data-line (DL) metal regions; and a conductive layer formed on the passivation layer. The passivation layer has a first, second and third vias for respectively exposing the partial surfaces of the source, drain and DL metal regions. The first, second and third vias are filled with the conductive layer, so that the DL and source metal regions are connected via the conductive layer.
摘要翻译：薄膜晶体管包括形成在基板上的栅电极; 覆盖栅电极的栅极绝缘层; 设置在栅极绝缘层上和栅电极上方的非晶硅（a-Si）区; 形成在a-Si区上的掺杂a-Si区; 源极和漏极金属区域分别形成在掺杂的a-Si区域和栅电极上方，并与a-Si区域隔离; 形成在所述栅极绝缘层上并覆盖所述源极，漏极和数据线（DL）金属区域的钝化层; 以及形成在钝化层上的导电层。钝化层具有用于分别暴露源极，漏极和DL金属区域的部分表面的第一，第二和第三通孔。第一，第二和第三通孔填充有导电层，使得DL和源极金属区域经由导电层连接。

9. 发明授权

US07074630B2 Method of forming light emitter layer 有权
标题翻译：形成光发射层的方法
公开(公告)号：US07074630B2
公开(公告)日：2006-07-11
申请号：US10441189
申请日：2003-05-20
申请人： Ting-Chang Chang , Po-Tsun Liu
发明人： Ting-Chang Chang , Po-Tsun Liu
IPC分类号： H01L21/00
CPC分类号： H05B33/22 , B82Y10/00 , B82Y20/00 , B82Y30/00 , H01L33/06 , H01L33/18 , H01L33/34 , Y10T428/25
摘要： A light emitting layer including a quantum structure and the forming method of forming the same is provided. The forming method includes several steps. At first, a compound dielectric layer forms, including a dielectric layer and an impure dielectric layer, which comprises major elements and impurities. The compound dielectric layer is treated to drive the impurities to form the quantum structure in the dielectric layer according to the difference in characteristic between the major elements and impurities. For example, oxidizing the major elements to drive the impurities of the impure dielectric layer to form the quantum structure inside the dielectric layer, because the oxidizing capability of the major elements is stronger than that of the impurities. The quantum structure and compound dielectric layer construct the light emitting layer.
摘要翻译：提供了包括量子结构的发光层及其形成方法。成型方法包括几个步骤。首先，形成包括电介质层和不纯的介电层的复合电介质层，其包含主要元素和杂质。根据主要元素和杂质之间的特性差，处理复合电介质层以驱动杂质以在电介质层中形成量子结构。例如，氧化主要元素以驱动不纯的介电层的杂质以在电介质层内形成量子结构，因为主要元素的氧化能力比杂质的氧化能力更强。量子结构和复合电介质层构成发光层。

10. 发明授权

US06635967B2 Air gap semiconductor structure and method of manufacture 有权
公开(公告)号：US06635967B2
公开(公告)日：2003-10-21
申请号：US09761943
申请日：2001-01-17
申请人： Ting-Chang Chang , Yi-Shien Mor , Po-Tsun Liu
发明人： Ting-Chang Chang , Yi-Shien Mor , Po-Tsun Liu
IPC分类号： H01L2900
CPC分类号： H01L21/7682
摘要： An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.

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