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1. 发明授权

US5331215A Electrically adaptable neural network with post-processing circuitry 失效
标题翻译：具有后处理电路的电适应神经网络
公开(公告)号：US5331215A
公开(公告)日：1994-07-19
申请号：US922535
申请日：1992-07-30
申请人： Timothy P. Allen , Janeen D. W. Anderson , Carver A. Mead , Federico Faggin , John C. Platt , Michael F. Wall
发明人： Timothy P. Allen , Janeen D. W. Anderson , Carver A. Mead , Federico Faggin , John C. Platt , Michael F. Wall
IPC分类号： G06N3/063 , H01L27/06 , H03F1/02 , H03F1/30 , H03F3/45 , H03K19/0948
CPC分类号： H03F1/303 , G06N3/063 , H01L27/0629 , H03F1/0261 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.
摘要翻译：根据本发明的突触阵列包括多个电适应元件。可以通过施加产生的第一和第二电控制信号将电子放置在与至少一个MOS绝缘栅场效应晶体管（通常是晶体管的栅极）相关联的每个电适应元件中的浮动节点上并从其移除，响应于适配信号。对一行中所有突触元素的输入连接到公共行输入行。将输入到列中的所有突触元素的调整连接到公共列适应线。提供给列中所有放大器的电流通常由感测线提供。为了适应本发明的M行×N列矩阵中的突触元素，要将矩阵的给定列n适应的电压放置在输入电压线上，并且列n中的突触元素然后通过在第n列的适应线上断言适配信号同时进行调整。用于适配连续列的输入电压的矢量可以顺序地放置在行输入电压线上，并且用于通过在适当的列适配线上断言适配信号来适应突触元件的列，直到整个阵列电气适配。在每个突触元件已经适应之后，当突触元件的输入端的电压等于突触元件适应的电压时，流过它的电流将被最大化。电气适应性的胜者总线电路的输入连接到阵列的列感测线。

2. 发明授权

US5270963A Method and apparatus for performing neighborhood operations on a processing plane 失效
标题翻译：在处理平面上执行邻域操作的方法和装置
公开(公告)号：US5270963A
公开(公告)日：1993-12-14
申请号：US549423
申请日：1990-07-06
申请人： Timothy P. Allen , Michael F. Wall , Federico Faggin
发明人： Timothy P. Allen , Michael F. Wall , Federico Faggin
IPC分类号： G06N3/063 , G06T5/20 , G06G7/16
CPC分类号： G06K9/605 , G06K9/00986 , G06K9/56 , G06N3/0635 , G06T5/20
摘要： The present invention is a method and apparatus for performing neighborhood processing operations on an n dimensional processing plane. In a simple, two dimensional, example, an M by N processing plane is successively scanned by rows. The output information from each row is presented on column lines. The analog data resulting from a fixed number of successive scans are temporarily held in a multi-stage analog buffer. A computing array is configured to perform the neighborhood operations or other limited co-operand operations on the shifted data. The computing array examines information from a slice made up of selected numbers of successive rows of the entire array, performs the operations on that portion, and provides a series of output signals representative of the result. The analog buffer is pipelined; information from a new row represents only a single row of new data and the contents of the latch stage containing the oldest information is replaced with this new analog data, causing the information from the transducers of the oldest row to be lost. The operation is then performed on the new slice. This sequence is repeated until all representative slices of the total array have had the neighborhood operations performed on them.
摘要翻译：本发明是一种用于在n维处理平面上执行邻域处理操作的方法和装置。在简单的二维例子中，逐行扫描M×N处理平面。来自每一行的输出信息都列在列线上。由固定数量的连续扫描产生的模拟数据暂时保存在多级模拟缓冲器中。计算阵列被配置为对移位的数据执行邻域操作或其他有限的协同操作数操作。计算阵列检查来自由整个阵列的选定数目的连续行组成的切片的信息，对该部分执行操作，并提供表示结果的一系列输出信号。模拟缓冲器是流水线的; 来自新行的信息仅代表单行新数据，并且包含最旧信息的锁存级的内容被该新的模拟数据替代，导致来自最旧行的换能器的信息丢失。然后在新切片上执行操作。重复该顺序，直到总阵列的所有代表性切片都对它们执行邻域操作。

3. 发明授权

US5160899A Adaptable MOS current mirror 失效
标题翻译：适应MOS电流镜
公开(公告)号：US5160899A
公开(公告)日：1992-11-03
申请号：US781503
申请日：1991-10-22
申请人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
发明人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
IPC分类号： G06N3/063 , H01L27/06 , H03F1/02 , H03F1/30 , H03F3/45
CPC分类号： G06N3/063 , H01L27/0629 , H03F1/0261 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.
摘要翻译：适应电流镜包括第一和第二MOS晶体管。第一个MOS晶体管的栅极连接到其漏极。 MOS电容器结构串联连接在第一MOS晶体管的栅极和第二MOS晶体管的栅极之间。电子可以通过施加第一和第二电气控制信号，以模拟方式从与第二MOS晶体管（通常是晶体管的栅极）相关联的浮动节点放置和去除。第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。可以采用与多个载流线路通信的多个适应电流镜，以指示最流动的多个通电线路中的一个的输出。

4. 发明授权

US5119038A CMOS current mirror with offset adaptation 失效
标题翻译：具有偏移适应的CMOS电流镜
公开(公告)号：US5119038A
公开(公告)日：1992-06-02
申请号：US650577
申请日：1991-02-04
申请人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
发明人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
IPC分类号： G06N3/063 , H01L27/06 , H03F1/02 , H03F1/30 , H03F3/45
CPC分类号： H03F1/303 , G06N3/063 , H01L27/0629 , H03F1/0261 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An MOS current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures in order to adapt the current mirror to supply a desired output current when a particular input calibration current is present.
摘要翻译： MOS电流镜包括浮动节点，在该浮动节点上，可以通过控制信号和电半导体结构从中传输电子，以便在存在特定输入校准电流时使电流镜适应于提供期望的输出电流。

5. 发明授权

US5146106A CMOS winner-take all circuit with offset adaptation 失效
标题翻译： CMOS优胜者 - 采用具有偏移适配的所有电路
公开(公告)号：US5146106A
公开(公告)日：1992-09-08
申请号：US650959
申请日：1991-02-05
申请人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
发明人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
IPC分类号： G06N3/063 , H01L27/06 , H03F1/02 , H03F1/30 , H03F3/45
CPC分类号： H01L27/0629 , G06N3/063 , H03F1/0261 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.
摘要翻译：可适应的MOS优胜者采取所有电路包括多个适应电流镜。每个可适应电流镜包括浮动节点，电子可以通过控制信号和电半导体结构传输到该浮动节点上。通过施加第一和第二电控制信号，电子可以以模拟的方式放置在与至少一个MOS绝缘栅场效应晶体管（通常是晶体管的栅极）相关联的浮动节点上并从其移除。第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。

6. 发明授权

US5059920A CMOS amplifier with offset adaptation 失效
标题翻译：具有偏移适配的CMOS放大器
公开(公告)号：US5059920A
公开(公告)日：1991-10-22
申请号：US525764
申请日：1990-05-18
申请人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
发明人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
IPC分类号： G06N3/063 , H01L27/06 , H03F1/02 , H03F1/30 , H03F3/45
CPC分类号： H03F1/0261 , G06N3/063 , H01L27/0629 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted.An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An electrical learning means allows the floating node to be charged or discharged to a voltage which effectively cancels the input offset voltage.
摘要翻译：通过施加第一和第二电气控制信号，电子可以以模拟方式放置在与至少一个MOS晶体管（通常是晶体管的栅极）相关联的浮动节点上并从其移除。第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。模拟MOS集成电路包括具有大于1的增益的放大器电路。该放大器电路的一级的反相输入是形成至少一个MOS晶体管的栅极的浮动节点。第一个电容将电路的输入耦合到该浮动节点。提供电气半导体结构用于从浮动栅极线性地添加和去除电荷，从而允许放大器的偏移电压被适配。具有随机输入偏移电压的集成电路放大器是可适应的，使得可以抵消输入偏移电压。反相输入节点是浮动输入节点，并通过第一电容器耦合到输入信号源。第二电容器连接在放大器的输出端和浮动节点之间。电学习装置允许浮动节点被充电或放电到有效地抵消输入偏移电压的电压。

7. 发明授权

US5165054A Circuits for linear conversion between currents and voltages 失效
标题翻译：用于电流和电压之间线性转换的电路
公开(公告)号：US5165054A
公开(公告)日：1992-11-17
申请号：US629470
申请日：1990-12-18
申请人： John C. Platt , Michael F. Wall , Glenn E. Gribble , Carver A. Mead
发明人： John C. Platt , Michael F. Wall , Glenn E. Gribble , Carver A. Mead
IPC分类号： H03F3/30
CPC分类号： H03F3/3022 , H03F3/3001 , H03F2203/30006 , H03F2203/30009 , H03F2203/30084 , H03F2203/30117
摘要： A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.
摘要翻译：线性电压 - 电流转换器（LVCC）电路包括两个晶体管，一个P沟道和一个N沟道。输入电压被施加到两个晶体管的栅极。两个晶体管的漏极相连。 p型晶体管的源极连接到第一电压轨，并且N沟道的源极连接到具有较低电压的第二电压轨。输出是通过P沟道晶体管和N沟道晶体管的电流之差。线性电流 - 电压转换器（LCVC）电路类似于LVCC电路，只是晶体管的栅极连接到晶体管的漏极。输入电流被提供给排水管，输出电压是排水管的电压。

8. 发明授权

US5126685A Circuits for linear conversion between voltages and currents 失效
标题翻译：用于电压和电流之间线性转换的电路
公开(公告)号：US5126685A
公开(公告)日：1992-06-30
申请号：US746962
申请日：1991-08-19
申请人： John C. Platt , Michael F. Wall , Glenn E. Gribble , Carver A. Mead
发明人： John C. Platt , Michael F. Wall , Glenn E. Gribble , Carver A. Mead
IPC分类号： H03F3/30
CPC分类号： H03F3/3022 , H03F3/3001 , H03F2203/30006 , H03F2203/30009 , H03F2203/30084 , H03F2203/30117
摘要： A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.
摘要翻译：线性电压 - 电流转换器（LVCC）电路包括两个晶体管，一个P沟道和一个N沟道。输入电压被施加到两个晶体管的栅极。两个晶体管的漏极相连。 p型晶体管的源极连接到第一电压轨，并且N沟道的源极连接到具有较低电压的第二电压轨。输出是通过P沟道晶体管和N沟道晶体管的电流之差。线性电流 - 电压转换器（LCVC）电路类似于LVCC电路，只是晶体管的栅极连接到晶体管的漏极。输入电流被提供给排水管，输出电压是排水管的电压。

9. 发明授权

US5107149A Linear, continuous-time, two quadrant multiplier 失效
标题翻译：线性，连续时间，两象限乘数
公开(公告)号：US5107149A
公开(公告)日：1992-04-21
申请号：US746960
申请日：1991-08-19
申请人： John C. Platt , Michael F. Wall , Glenn E. Gribble , Carver A. Mead
发明人： John C. Platt , Michael F. Wall , Glenn E. Gribble , Carver A. Mead
IPC分类号： H03F3/30
CPC分类号： H03F3/3022 , H03F3/3001 , H03F2203/30006 , H03F2203/30009 , H03F2203/30084 , H03F2203/30117
摘要： A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.
摘要翻译：线性电压 - 电流转换器（LVCC）电路包括两个晶体管，一个P沟道和一个N沟道。输入电压被施加到两个晶体管的栅极。两个晶体管的漏极相连。 p型晶体管的源极连接到第一电压轨，并且N沟道的源极连接到具有较低电压的第二电压轨。输出是通过P沟道晶体管和N沟道晶体管的电流之差。线性电流 - 电压转换器（LCVC）电路类似于LVCC电路，只是晶体管的栅极连接到晶体管的漏极。输入电流被提供给排水管，输出电压是排水管的电压。

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