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1. 发明申请

US20100005375A1 CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK 失效
标题翻译：循环冗余码用于高速串行链路
公开(公告)号：US20100005375A1
公开(公告)日：2010-01-07
申请号：US12166207
申请日：2008-07-01
申请人： Timothy J. Dell , Kevin C. Gower , Luis A. Lastras-Montano
发明人： Timothy J. Dell , Kevin C. Gower , Luis A. Lastras-Montano
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H04L1/0056 , G06F11/10
摘要： A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.
摘要翻译：一种用于提供用于高速串行链路的循环冗余码（CRC）的系统和方法。该系统包括级联互连存储器系统，其包括存储器控制器，存储器集线器设备和下游链路。下游链路与存储器控制器和存储器集线器设备通信，并且包括用于将多个传输下行帧从存储器控制器发送到存储器集线器设备的至少十三个信号通道。下游帧的一部分包括用于检测下游帧中的错误的下行CRC位。下行CRC比特能够检测到车道故障，转移故障和高达五位随机错误中的任何一个。

2. 发明申请

US20090006886A1 SYSTEM AND METHOD FOR ERROR CORRECTION AND DETECTION IN A MEMORY SYSTEM 有权
标题翻译：用于记忆系统中错误校正和检测的系统和方法
公开(公告)号：US20090006886A1
公开(公告)日：2009-01-01
申请号：US11769929
申请日：2007-06-28
申请人： James A. O'Connor , Luis A. Lastras-Montano , Luis C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
发明人： James A. O'Connor , Luis A. Lastras-Montano , Luis C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
IPC分类号： G06F11/20
CPC分类号： G06F11/108 , G06F2211/1045 , G06F2211/1057 , G06F2211/1064
摘要： A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.
摘要翻译：一种用于存储系统中的纠错和检测的系统和方法。该系统包括存储器控制器，多个存储器模块和机构。存储器模块与存储器控制器和多个存储器件通信。该机制检测到其中一个内存模块出现故障，可能与其他内存模块上的内存设备故障一致。该机制允许内存系统在内存模块故障和内存设备故障的情况下继续运行不受损坏。

3. 发明授权

US08201069B2 Cyclical redundancy code for use in a high-speed serial link 失效
标题翻译：用于高速串行链路的循环冗余码
公开(公告)号：US08201069B2
公开(公告)日：2012-06-12
申请号：US12166207
申请日：2008-07-01
申请人： Timothy J. Dell , Kevin C. Gower , Luis A. Lastras-Montano
发明人： Timothy J. Dell , Kevin C. Gower , Luis A. Lastras-Montano
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H04L1/0056 , G06F11/10
摘要： A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.
摘要翻译：一种用于提供用于高速串行链路的循环冗余码（CRC）的系统和方法。该系统包括级联互连存储器系统，其包括存储器控制器，存储器集线器设备和下游链路。下游链路与存储器控制器和存储器集线器设备通信，并且包括用于将多个传输下行帧从存储器控制器发送到存储器集线器设备的至少十三个信号通道。下游帧的一部分包括用于检测下游帧中的错误的下行CRC位。下行CRC比特能够检测到车道故障，转移故障和高达五位随机错误中的任何一个。

4. 发明授权

US08041990B2 System and method for error correction and detection in a memory system 有权
标题翻译：用于存储系统中纠错和检测的系统和方法
公开(公告)号：US08041990B2
公开(公告)日：2011-10-18
申请号：US11769929
申请日：2007-06-28
申请人： James A. O'Connor , Luis A. Lastras-Montano , Luis C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
发明人： James A. O'Connor , Luis A. Lastras-Montano , Luis C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
IPC分类号： G06F11/00
CPC分类号： G06F11/108 , G06F2211/1045 , G06F2211/1057 , G06F2211/1064
摘要： A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.
摘要翻译：一种用于存储系统中的纠错和检测的系统和方法。该系统包括存储器控制器，多个存储器模块和机构。存储器模块与存储器控制器和多个存储器件通信。该机制检测到其中一个内存模块出现故障，可能与其他内存模块上的内存设备故障一致。该机制允许内存系统在内存模块故障和内存设备故障的情况下继续运行不受损坏。

5. 发明授权

US08041989B2 System and method for providing a high fault tolerant memory system 有权
标题翻译：提供高容错存储系统的系统和方法
公开(公告)号：US08041989B2
公开(公告)日：2011-10-18
申请号：US11769936
申请日：2007-06-28
申请人： Luis A. Lastras-Montano , James A. O'Connor , Luiz C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
发明人： Luis A. Lastras-Montano , James A. O'Connor , Luiz C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
IPC分类号： G06F11/00
CPC分类号： G06F11/1044 , G11C5/04 , G11C29/4401 , G11C29/81 , G11C2029/0409 , G11C2029/0411
摘要： A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.
摘要翻译：一种用于提供高容错存储器系统的系统和方法。该系统包括具有存储器控制器，多个存储器模块和机构的存储器系统。多个存储器模块与存储器控制器和多个存储器件通信。多个存储器件包括用于提供存储器件备用能力的至少一个备用存储器件。该机制用于检测存储器模块中的一个已经失败，可能与另一个存储器模块上的存储器件故障重合。该机制允许存储器系统在存在存储器模块故障和可能的存储器件故障的情况下继续运行不受损害。

6. 发明申请

US20090006900A1 SYSTEM AND METHOD FOR PROVIDING A HIGH FAULT TOLERANT MEMORY SYSTEM 有权
标题翻译：用于提供高容错记忆体系统的系统和方法
公开(公告)号：US20090006900A1
公开(公告)日：2009-01-01
申请号：US11769936
申请日：2007-06-28
申请人： Luis A. Lastras-Montano , James A. O'Connor , Luiz C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
发明人： Luis A. Lastras-Montano , James A. O'Connor , Luiz C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
IPC分类号： G06F11/00
CPC分类号： G06F11/1044 , G11C5/04 , G11C29/4401 , G11C29/81 , G11C2029/0409 , G11C2029/0411
摘要： A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.
摘要翻译：一种用于提供高容错存储器系统的系统和方法。该系统包括具有存储器控制器，多个存储器模块和机构的存储器系统。多个存储器模块与存储器控制器和多个存储器件通信。多个存储器件包括用于提供存储器件备用能力的至少一个备用存储器件。该机制用于检测存储器模块中的一个已经失败，可能与另一个存储器模块上的存储器件故障重合。该机制允许存储器系统在存在存储器模块故障和可能的存储器件故障的情况下继续运行不受损害。

7. 发明申请

US20110320914A1 ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM 有权
标题翻译：冗余存储系统中的错误校正和检测
公开(公告)号：US20110320914A1
公开(公告)日：2011-12-29
申请号：US12822503
申请日：2010-06-24
申请人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
发明人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , G06F11/108
摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.
摘要翻译：在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害失败。

8. 发明申请

US20110320869A1 HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM 有权
标题翻译：在冗余存储系统中均衡恢复
公开(公告)号：US20110320869A1
公开(公告)日：2011-12-29
申请号：US12822964
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
IPC分类号： G06F11/07 , G06F11/14
CPC分类号： G06F11/1666 , G06F11/1044 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.
摘要翻译：在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动至少在存储器通道的第一子集上进行新的操作。存储器系统能够与存储器通道的第一子集一起操作。

9. 发明申请

US20110320864A1 HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM 有权
标题翻译：冗余存储系统中的异构恢复
公开(公告)号：US20110320864A1
公开(公告)日：2011-12-29
申请号：US12822968
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
IPC分类号： G06F11/20 , G06F11/08 , G06F11/00
CPC分类号： G06F11/2053 , G06F11/073 , G06F11/0793 , G06F11/1004 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete.
摘要翻译：在包括存储器控制器，与存储器控制器通信的多个存储器通道，配置用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供异构恢复。错误恢复机制被配置为用于接收故障存储器通道的通知，用于在其他存储器通道执行正常的系统操作时对故障存储器通道执行恢复操作，以使恢复的通道与其它存储器通道重新进入操作模式，存储操作，用于继续标记恢复的通道以防止陈旧的数据，用于在恢复操作完成之后去除任何陈旧的数据，以及用于去除恢复的通道上的标记，以允许所有存储器通道的正常系统操作，删除，以响应删除任何陈旧的数据完成。

10. 发明授权

US08086783B2 High availability memory system 有权
标题翻译：高可用性内存系统
公开(公告)号：US08086783B2
公开(公告)日：2011-12-27
申请号：US12390731
申请日：2009-02-23
申请人： James A. O'Connor , Kevin C. Gower , Luis A. Lastras-Montano , Warren E. Maule
发明人： James A. O'Connor , Kevin C. Gower , Luis A. Lastras-Montano , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F11/1004 , G06F12/0886
摘要： A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.
摘要翻译：提供了高可用性的内存系统。存储器系统包括多个存储器通道。每个存储器通道包括至少一个存储器模块，其中存储器件被组织为耦合到存储器设备总线段的部分等级。每个部分等级包括作为存储器设备总线段的子集上的子信道可访问的存储器件的子集。存储器系统还包括与多个存储器通道通信的存储器控制器。存储器控制器通过存储器通道分配访问请求以访问完整等级。完整等级包括在独立内存通道上的至少两个部分等级。可以同时访问公共内存模块上的部分排名。存储器模块可以在至少两个可同时访问的部分等级之间使用至少一个校验和存储器设备作为专用校验和存储器设备或共享校验和存储器设备。

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