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1. 发明授权

US07760669B2 Method and apparatus for preventing starvation in a slotted ring data communications network 失效
标题翻译：用于防止在时隙环数据通信网络中的饥饿的方法和装置
公开(公告)号：US07760669B2
公开(公告)日：2010-07-20
申请号：US11426746
申请日：2006-06-27
申请人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
发明人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
IPC分类号： H04L12/43
CPC分类号： H04L12/4035 , H04L12/423
摘要： In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
摘要翻译：在时隙环网络中，节点可以用任何未预留的时隙发送不可更新的时隙预留。该预约限制其他节点在时隙中发送新的分组。当插槽返回环到保留节点时，插槽将可用。优选地，响应于预留节点中的饥饿状况做出预约，其可以以各种方式中的任一种来检测。在可选增强中，预留识别预留节点，并且如果新分组将在保留节点处或之前到达其目的地，则环上的另一个节点可以自由地在保留时隙中发送新分组，并且因此不会干扰预订。

2. 发明授权

US07826399B2 Structure for preventing starvation in a slotted ring data communications network 失效
标题翻译：用于在时隙环数据通信网络中防止饥饿的结构
公开(公告)号：US07826399B2
公开(公告)日：2010-11-02
申请号：US12042612
申请日：2008-03-05
申请人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
发明人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
IPC分类号： H04L12/43
CPC分类号： H04L12/4035 , H04L12/66
摘要： A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
摘要翻译：为时隙环网提供了一种设计结构，其中节点可以用任何未预留的时隙发送不可再生的时隙预留。该预约限制其他节点在时隙中发送新的分组。当插槽返回环到保留节点时，插槽将可用。优选地，响应于预留节点中的饥饿状况做出预约，其可以以各种方式中的任一种来检测。在可选增强中，预留识别预留节点，并且如果新分组将在保留节点处或之前到达其目的地，则环上的另一个节点可以自由地在保留时隙中发送新分组，并且因此不会干扰预订。

3. 发明申请

US20070297441A1 Method and Apparatus for Preventing Starvation in a Slotted Ring Data Communications Network 失效
标题翻译：用于在开槽环数据通信网络中预防饥饿的方法和装置
公开(公告)号：US20070297441A1
公开(公告)日：2007-12-27
申请号：US11426746
申请日：2006-06-27
申请人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
发明人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
IPC分类号： H04L12/43
CPC分类号： H04L12/4035 , H04L12/423
摘要： In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
摘要翻译：在时隙环网络中，节点可以用任何未预留的时隙发送不可更新的时隙预留。该预约限制其他节点在时隙中发送新的分组。当插槽返回环到保留节点时，插槽将可用。优选地，响应于预留节点中的饥饿状况做出预约，其可以以各种方式中的任一种来检测。在可选增强中，预留识别预留节点，并且如果新分组将在保留节点处或之前到达其目的地，则环上的另一个节点可以自由地在保留时隙中发送新分组，并且因此不会干扰预订。

4. 发明申请

US20080159176A1 Structure for Preventing Starvation in a Slotted Ring Data Communications Network 失效
标题翻译：在一个开槽环数据通信网络中预防饥饿的结构
公开(公告)号：US20080159176A1
公开(公告)日：2008-07-03
申请号：US12042612
申请日：2008-03-05
申请人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
发明人： Timothy Hume Heil , Michael Steven Siegel , Jeffrey R. Summers , Steven Paul VanderWiel
IPC分类号： H04L12/28
CPC分类号： H04L12/4035 , H04L12/66
摘要： A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.
摘要翻译：为时隙环网提供了一种设计结构，其中节点可以用任何未预留的时隙发送不可再生的时隙预留。该预约限制其他节点在时隙中发送新的分组。当插槽返回环到保留节点时，插槽将可用。优选地，响应于预留节点中的饥饿状况做出预约，其可以以各种方式中的任一种来检测。在可选增强中，预留识别预留节点，并且如果新分组将在保留节点处或之前到达其目的地，则环上的另一个节点可以自由地在保留时隙中发送新分组，并且因此不会干扰预订。

5. 发明申请

US20120124291A1 Secondary Cache Memory With A Counter For Determining Whether to Replace Cached Data 审中-公开
标题翻译：具有用于确定是否替换缓存数据的计数器的二级缓存内存
公开(公告)号：US20120124291A1
公开(公告)日：2012-05-17
申请号：US12946883
申请日：2010-11-16
申请人： Heather D. Achilles , Timothy Hume Heil , Anil Krishna , Nicholas David Lindberg , Steven Paul VanderWiel , Shaul Yifrach
发明人： Heather D. Achilles , Timothy Hume Heil , Anil Krishna , Nicholas David Lindberg , Steven Paul VanderWiel , Shaul Yifrach
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0888 , G06F12/122
摘要： A selective cache includes a set configured to receive data evicted from a number of primary sets of a primary cache. The selective cache also includes a counter associated with the set. The counter is configured to indicate a frequency of access to data within the set. A decision whether to replace data in the set with data from one of the primary sets is based on a value of the counter.
摘要翻译：选择性高速缓存包括被配置为接收从主要高速缓存的多个主组驱逐的数据的集合。选择性高速缓存还包括与该组相关联的计数器。计数器被配置为指示访问集合内的数据的频率。是否使用来自主要集合之一的数据替换集合中的数据的决定是基于计数器的值。

6. 发明申请

US20100271071A1 Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks 有权
标题翻译：多层半导体堆叠的通用层间互连
公开(公告)号：US20100271071A1
公开(公告)日：2010-10-28
申请号：US12431259
申请日：2009-04-28
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
IPC分类号： H01L25/00 , G06F17/50
CPC分类号： G06F17/5068 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2224/05599 , H01L2224/05099
摘要： A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.
摘要翻译：电路布置和方法利用多层半导体堆叠中的通用的标准化层间互连，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。基于每个电路层中的层间界面区域的标准化布置以及与层间总线相关联的电导体的标准化布置，每个电路层可以使用标准化模板来设计，在该模板上设计实现已经提供了层间总线，从而简化了电路层设计和功能单元与层间总线的互连。此外，可以在半导体堆叠内定义垂直取向的超节点，以提供多个独立运行的节点，其具有布置在堆叠的多个电路层中的功能单元。

7. 发明申请

US20130009324A1 UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS 有权
标题翻译：用于多层半导体堆叠的通用层间互连
公开(公告)号：US20130009324A1
公开(公告)日：2013-01-10
申请号：US13618600
申请日：2012-09-14
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel , Patrick Ronald Varekamp
IPC分类号： H01L23/522 , H01L23/48 , G06F17/50
CPC分类号： G06F17/5068 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2224/05599 , H01L2224/05099
摘要： An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.
摘要翻译：一种装置，程序产品和方法有助于在多层半导体堆叠中结合通用的标准化层间互连的多层电路装置的设计，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。

8. 发明申请

US20120187570A1 HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS 有权
公开(公告)号：US20120187570A1
公开(公告)日：2012-07-26
申请号：US13422606
申请日：2012-03-16
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06544
摘要： A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

9. 发明授权

US08736068B2 Hybrid bonding techniques for multi-layer semiconductor stacks 有权
标题翻译：用于多层半导体堆叠的混合键合技术
公开(公告)号：US08736068B2
公开(公告)日：2014-05-27
申请号：US13422606
申请日：2012-03-16
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel
IPC分类号： H01L21/00 , H01L25/065 , H01L25/00 , H01L25/18
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06544
摘要： A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.
摘要翻译：电路布置和方法利用混合键合技术，其将晶片 - 晶片接合工艺与芯片芯片和/或晶片 - 晶片接合工艺组合以形成多层半导体堆叠，例如通过将由一个或多个子组件使用芯片芯片和/或芯片 - 晶片接合工艺与其它子组件和/或芯片一起进行晶片 - 晶片接合。通过这样做，可以利用芯片芯片和芯片 - 晶片结合技术的优点来利用诸如更高互连密度的晶片 - 晶片接合技术的优点，例如混合和匹配具有不同尺寸，长宽比的芯片和功能。

10. 发明授权

US08293578B2 Hybrid bonding techniques for multi-layer semiconductor stacks 失效
标题翻译：用于多层半导体堆叠的混合键合技术
公开(公告)号：US08293578B2
公开(公告)日：2012-10-23
申请号：US12911879
申请日：2010-10-26
申请人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel
发明人： Gerald K. Bartley , Russell Dean Hoover , Charles Luther Johnson , Steven Paul VanderWiel
IPC分类号： H01L23/538 , H01L21/50
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06544
摘要： A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.
摘要翻译：电路布置和方法利用混合键合技术，其将晶片 - 晶片接合工艺与芯片芯片和/或晶片 - 晶片接合工艺组合以形成多层半导体堆叠，例如通过将由一个或多个子组件使用芯片芯片和/或芯片 - 晶片接合工艺与其它子组件和/或芯片一起进行晶片 - 晶片接合。通过这样做，可以利用芯片芯片和芯片 - 晶片结合技术的优点来利用诸如更高互连密度的晶片 - 晶片接合技术的优点，例如混合和匹配具有不同尺寸，长宽比的芯片和功能。

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