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    • 2. 发明授权
      US06185620B2 Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion 失效
    • Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion
    • 单芯片协议引擎和数据格式化装置，用于离线主机内存到本地存储器的传输和转换
    • US06185620B2
    • 2001-02-06
    • US09054849
    • 1998-04-03
    • David M. Weber , Timothy E. Hoglund , Stephen M. Johnson , John M. Adams , Mark A. Reber
    • David M. Weber , Timothy E. Hoglund , Stephen M. Johnson , John M. Adams , Mark A. Reber
    • G06F1100
    • H04L49/901 , H04L29/06 , H04L49/90 , H04L49/9031 , H04L69/12
    • A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received. A link control unit is provided in which loop management is provided when the host is connected to a loop. Management of the loop includes implementing mechanisms to initiate acquisition of the loop and initiate a release of the loop in response to conditions in which data is received and transmitted by the host and by other nodes on the loop.
    • 一种用于通过将主机连接到节点的结构将数据从主机传送到节点的方法和装置。 提供了一种芯片架构，其中协议引擎提供用于传送数据的船舶处理，使得来自芯片中的各种组件的频繁中断可以被处理而无需主机处理器的干预。 另外，提供上下文管理器来发送和接收数据。 协议引擎创建传输活动的列表，该列表由上下文管理器遍历，后者又以独立于协议引擎的方式执行列出的活动。 在接收数据时，上下文管理器提供一种机制来处理来自各种源的数据帧，而不需要来自协议引擎的干预。 当接收到数据时，上下文管理器能够处理来自不同来源的帧，这些帧到达无序。 另外，上下文管理器还确定序列中的所有帧何时已被接收。 提供了一种链路控制单元，其中当主机连接到环路时，提供循环管理。 循环的管理包括执行机制以启动循环的获取并且响应于由主机和循环中的其他节点接收和发送数据的条件来启动循环的释放。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5777987A Method and apparatus for using multiple FIFOs to improve flow control and routing in a communications receiver 失效
    • Method and apparatus for using multiple FIFOs to improve flow control and routing in a communications receiver
    • 使用多个FIFO来改善通信接收机中的流量控制和路由的方法和装置
    • US5777987A
    • 1998-07-07
    • US580947
    • 1995-12-29
    • John M. Adams , Timothy E. Hoglund , Stephen M. Johnson , Mark A. Reber , David M. Weber
    • John M. Adams , Timothy E. Hoglund , Stephen M. Johnson , Mark A. Reber , David M. Weber
    • H04L29/02 , H04L12/56 , H04J3/00
    • H04L47/30 , H04L47/10 , H04L47/26
    • A method and associated apparatus for using a primary FIFO and one or more secondary FIFOs in parallel to simplify flow control and routing in packet communication operations wherein at least one FIFO (buffer) is associated with each of a plurality of receiving nodes or components within a receiving node. The present invention applies received packets simultaneously to a primary FIFO and to all associated secondary FIFOs in the receiver of a packet communications link. After receipt of a packet, the packet is removed from any secondary FIFOs which correspond to receiver nodes or components to which the packet was not routed. For all receiving nodes or components to which the packet was routed, if the packet was stored in each associated secondary FIFO without overflow, then the packet is also purged from the primary FIFO. If any secondary FIFO overflowed by storage of the received packet, then the packet is purged from the overflowed FIFO and the packet remains stored in the primary FIFO for further processing. Flow control signals are generated and applied to the transmitting source as required in accordance with the status of the primary FIFO. The secondary FIFOs are not directly relevant to flow control logic. The receiving component corresponding to each secondary FIFO locates the next packet for processing by inspecting the associated secondary FIFO as well as the primary FIFO if the secondary FIFO overflowed. These methods and apparatus simplify flow control and routing control in packetized communication receivers.
    • 一种用于并行地使用主FIFO和一个或多个辅助FIFO以简化在分组通信操作中的流控制和路由的方法和相关联的装置，其中至少一个FIFO（缓冲器）与多个接收节点中的每一个相关联， 接收节点。 本发明将接收到的分组同时应用于主FIFO和分组通信链路的接收机中的所有相关联的辅助FIFO。 在接收到分组之后，从与分组未被路由到的接收机节点或组件对应的任何辅助FIFO中移除分组。 对于分组路由到的所有接收节点或组件，如果分组存储在每个相关联的辅助FIFO中，而不会溢出，则该分组也从主FIFO中清除。 如果任何辅助FIFO通过存储接收的分组溢出，则从溢出的FIFO中清除分组，并且分组保持存储在主FIFO中用于进一步处理。 根据主FIFO的状态，根据需要生成流量控制信号并将其应用于发送源。 二级FIFO与流量控制逻辑不直接相关。 对应于每个辅助FIFO的接收组件通过检查相关联的辅助FIFO以及主FIFO溢出时定位下一个数据包进行处理。 这些方法和装置简化了分组通信接收机中的流量控制和路由控制。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5761424A Method and apparatus for programmable filtration and generation of information in packetized communication systems 失效
    • Method and apparatus for programmable filtration and generation of information in packetized communication systems
    • 用于可编程过滤和在分组通信系统中生成信息的方法和装置
    • US5761424A
    • 1998-06-02
    • US580955
    • 1995-12-29
    • John M. Adams , Timothy E. Hoglund , Stephen M. Johnson , Mark A. Reber , David M. Weber
    • John M. Adams , Timothy E. Hoglund , Stephen M. Johnson , Mark A. Reber , David M. Weber
    • H04L12/56 , G06F15/17 , H04L29/06 , G06F15/16
    • H04L29/06 , G06F15/17
    • A method and associated apparatus for automating the filtration and generation of information in a packetized communication system. A filtration table includes entries used in recognizing a valid packet received at a node in a communication system. A mask field in each entry is applied to appropriate fields in the packet (e.g. the ordered set as applied to Fibre Channel communication systems) to determine the validity of the packet with regard to the receiving node. Rules in a field of each entry further qualify the recognition of a received packet (e.g. ordered set) by testing the reception of the packet against other logical rules. Action fields in each record permit definition of actions to be invoked automatically (e.g. automatic adjustment of fill transmissions in Fibre Channel applications) in response to receipt and recognition of a particular packet. The set of packets recognized by the receiving node may be modified by adding, deleting, or modifying the entries in the filtration table. The programmable filtration thereby permits simple modifications to the protocol supported by the receiving node. Programmable generation capabilities of the present invention permit rapid integration of additional packets (e.g. ordered sets) transmitted in response to perceived packets in the receiving node. Programmable parameters in the receiving node permit automatic generation and transmission of packets in accordance with the parameter settings at the time of packet transmission.
    • 一种用于在分组化通信系统中自动化过滤和生成信息的方法和相关联的装置。 过滤表包括用于识别在通信系统中的节点处接收的有效分组的条目。 每个条目中的掩码字段被应用于分组中的适当字段（例如应用于光纤通道通信系统的有序集合），以确定分组关于接收节点的有效性。 通过根据其他逻辑规则测试分组的接收，每个条目的字段中的规则进一步限定了对接收到的分组（例如，有序集合）的识别。 每个记录中的动作字段允许响应于对特定分组的接收和识别而自动调用的动作的定义（例如，在光纤通道应用中自动调整填充传输）。 可以通过添加，删除或修改过滤表中的条目来修改由接收节点识别的分组集合。 可编程过滤因此允许对接收节点支持的协议的简单修改。 本发明的可编程生成能力允许快速集成响应于接收节点中的感知分组而发送的附加分组（例如有序集合）。 接收节点中的可编程参数允许根据分组传输时的参数设置自动生成和传输分组。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5146211A Bit mapped color cursor 失效
    • Bit mapped color cursor
    • 位映射颜色光标
    • US5146211A
    • 1992-09-08
    • US566014
    • 1990-08-10
    • John M. Adams , Brian K. Herbert , Stephen M. Johnson , Jamey L. Robbins
    • John M. Adams , Brian K. Herbert , Stephen M. Johnson , Jamey L. Robbins
    • G09G5/08
    • G09G5/08
    • An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor information controlling the generation of its outline and its color pattern. When accessed, this cursor control data is accessed from the non-displayed segment of the memory during each horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Location of the cursor within the video display is determined by a group of position registers which are loaded by the CPU with cursor position data during the vertical blank time. The position registers in conjunction with a group of counters coordinate the insertion of the cursor data into a byte stream of display data as it makes its way to the CRT screen. This display data is stored in the frame buffer and is transferred to the pixel output buffer. The display data in the pixel output buffer is subsequently interpreted into colors and intensities, and displayed on the CRT screen using known techniques. The vertical and horizontal locations of the cursor are synchronously incremented on a pixel by pixel basis during the scan of a frame buffer line. At the appropriate location, cursor data is multiplexed and/or logically combined with the bit stream of frame buffer data to overlay the cursor characteristics upon the video display data. The cursor data buffer can thereby be relatively small yet overlay a relatively large cursor with minimal manipulation by the computer controlling the video display.
    • 一种用于在从具有非显示但可寻址的存储器空间的帧缓冲器中操作的位映射视频显示系统的上下文中生成硬件光标的架构。 未显示的存储器的段被加载有控制其轮廓及其颜色模式的生成的光标信息。 当访问时，在光标覆盖的视频图案数据的光栅扫描之前的每个水平空白时间期间，从存储器的未显示段访问该光标控制数据。 视频显示中的光标的位置由在垂直空白时间期间由CPU加载光标位置数据的一组位置寄存器确定。 位置寄存器结合一组计数器协调将光标数据插入到显示数据的字节流中，当它进入CRT屏幕时。 该显示数据被存储在帧缓冲器中并被传送到像素输出缓冲器。 像素输出缓冲器中的显示数据随后被解释为颜色和强度，并使用已知技术在CRT屏幕上显示。 在帧缓冲线的扫描期间，光标的垂直和水平位置在逐个像素的基础上同步递增。 在适当的位置，光标数据被多路复用和/或逻辑地与帧缓冲器数据的比特流组合以将光标特性覆盖在视频显示数据上。 因此，光标数据缓冲器可以相对较小，但是通过控制视频显示的计算机的最小化操作覆盖相对大的光标。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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