专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08218364B2 Operation methods for memory cell and array for reducing punch through leakage 有权
标题翻译：用于减少穿孔渗漏的存储单元和阵列的操作方法
公开(公告)号：US08218364B2
公开(公告)日：2012-07-10
申请号：US13159413
申请日：2011-06-13
申请人： Lit-Ho Chong , Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
发明人： Lit-Ho Chong , Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
IPC分类号： G11C11/34
CPC分类号： G11C5/04 , G11C16/0416 , G11C16/10 , H01L27/11521 , H01L27/11568
摘要： An integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, each memory cell including two doped regions and a channel region therebetween, each pair of adjacent memory cells sharing a common doped region, each memory cell having a charge storage member over the channel region and a control gate over the charge storage member. A first word line is coupled to the memory cells in the same row, each of the memory cells designated as the Nth memory cell. Each of a plurality of bit lines is designated as the Nth bit line, the Nth bit line coupled to a doped region shared by the Nth memory cell and the (N−1)th memory cell. The integrated circuit also has a plurality of global bit lines, each of which coupled to two of the bit lines via a switch.
摘要翻译：集成电路包括具有以行和列排列的多个存储单元的存储器阵列，每个存储单元包括两个掺杂区和它们之间的沟道区，每对相邻的存储单元共用公共掺杂区，每个存储单元具有一个电荷存储部件，以及位于电荷存储部件上的控制栅极。第一字线耦合到相同行中的存储器单元，每个存储器单元被指定为第N个存储器单元。多个位线中的每一行被指定为第N位线，第N位线耦合到由第N存储器单元和第（N-1）个存储器单元共享的掺杂区域。集成电路还具有多个全局位线，每个位线经由开关耦合到两个位线。

2. 发明授权

US07864594B2 Memory apparatus and method thereof for operating memory 有权
标题翻译：用于操作存储器的存储装置及其方法
公开(公告)号：US07864594B2
公开(公告)日：2011-01-04
申请号：US12250766
申请日：2008-10-14
申请人： Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
发明人： Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10
摘要： A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced.
摘要翻译：提供了一种用于编程非易失性存储器单元的存储装置，控制器及其方法。存储装置包括多个存储单元，其中每个存储单元与相邻的存储单元共享源/漏区。该方法利用施加到两个存储单元之间的源极/漏极区域中的补偿电子流，以提供足够的电子流来编程两个存储器单元之一，即使在另一个存储单元具有较大的阈值电压的情况下，存储器单元的编程速度的偏差减小。

3. 发明申请

US20100176437A1 MEMORY ARRAY AND METHOD FOR MANUFACTURING AND OPERATING THE SAME 有权
标题翻译：存储器阵列及其制造和操作的方法
公开(公告)号：US20100176437A1
公开(公告)日：2010-07-15
申请号：US12352947
申请日：2009-01-13
申请人： Jyun-Siang Huang , Wen-Jer Tsai , Tien-Fan Ou
发明人： Jyun-Siang Huang , Wen-Jer Tsai , Tien-Fan Ou
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/11565 , H01L29/4234 , H01L29/792
摘要： The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.
摘要翻译：本发明提供一种存储器阵列。存储器阵列包括衬底，多个字线，电荷俘获结构，多个沟槽沟道和多个位线。字线位于衬底上，字线彼此平行。电荷捕获结构覆盖每条字线的表面。沟槽沟槽位于衬底之上，并且字线和沟槽沟槽交替布置，并且通过电荷捕获结构将每个沟槽沟道与相邻字线分开。位线位于字线之上，并且每个位线跨越每一个字线，并且每个沟道沟道电耦合到位线。

4. 发明申请

US20110079840A1 MEMORY CELL AND MANUFACTURING METHOD THEREOF AND MEMORY STRUCTURE 审中-公开
标题翻译：存储单元及其制造方法和存储器结构
公开(公告)号：US20110079840A1
公开(公告)日：2011-04-07
申请号：US12571692
申请日：2009-10-01
申请人： Jyun-Siang Huang , Wen-Jer Tsai , Tien-Fan Ou , Cheng-Hsien Cheng
发明人： Jyun-Siang Huang , Wen-Jer Tsai , Tien-Fan Ou , Cheng-Hsien Cheng
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/4983 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/40114 , H01L29/40117 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region.
摘要翻译：提供存储单元。存储单元包括衬底，隔离层，栅极，电荷存储结构，第一源极/漏极区，第二源极/漏极区和沟道层。隔离层设置在衬底上。栅极设置在隔离层上。电荷存储结构设置在隔离层和栅极上。第一源极/漏极区域设置在栅极两侧的电荷存储结构之上。第二源极/漏极区域设置在栅极顶部的电荷存储结构的上方。沟道层设置在栅极侧壁上的电荷存储结构上，并与第一源/漏区和第二源极/漏极区电连接。

5. 发明授权

US07723757B2 Vertical nonvolatile memory cell, array, and operation 有权
标题翻译：垂直非易失性存储单元，阵列和操作
公开(公告)号：US07723757B2
公开(公告)日：2010-05-25
申请号：US11774452
申请日：2007-07-06
申请人： Tien Fan Ou , Wen-Jer Tsai , Hsuan Ling Kao , Yi Ying Liao
发明人： Tien Fan Ou , Wen-Jer Tsai , Hsuan Ling Kao , Yi Ying Liao
IPC分类号： H01L29/74
CPC分类号： G11C16/0416 , G11C16/10 , H01L27/1026 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/7923 , H01L29/7926
摘要： A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的垂直非易失性存储单元包括具有三个节点的电荷控制结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

6. 发明申请

US20090116287A1 OPERATION METHODS FOR MEMORY CELL AND ARRAY THEREOF IMMUNE TO PUNCHTHROUGH LEAKAGE 有权
标题翻译：用于记忆细胞和阵列的操作方法免受漏洞的影响
公开(公告)号：US20090116287A1
公开(公告)日：2009-05-07
申请号：US12264893
申请日：2008-11-04
申请人： TIEN-FAN OU , Wen-Jer Tsai , Jyun-Siang Huang
发明人： TIEN-FAN OU , Wen-Jer Tsai , Jyun-Siang Huang
IPC分类号： G11C16/04 , H01L29/788 , G11C16/06
CPC分类号： G11C5/04 , G11C16/0416 , G11C16/10 , H01L27/11521 , H01L27/11568
摘要： An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell, wherein the third doped region is floating.
摘要翻译：集成电路包括包括第一单元和第二单元的存储单元结构。第一单元包括第一存储结构和衬底上的第一栅极。第一个门是第一个存储结构。第二单元包括第二存储结构和衬底上的第二栅极。第二个门是第二个存储结构。第一个门与第二个门分开。第一掺杂区域与第一单元相邻并且耦合到第一源极。第二掺杂区域被配置在衬底内且与第二单元相邻。第二掺杂区域耦合到第二源极。至少一个第三掺杂区域在第一单元和第二单元之间，其中第三掺杂区域是浮置的。

7. 发明授权

US08369148B2 Operation methods for memory cell and array thereof immune to punchthrough leakage 有权
标题翻译：记忆单元及其阵列的操作方法免于穿透泄漏
公开(公告)号：US08369148B2
公开(公告)日：2013-02-05
申请号：US12264893
申请日：2008-11-04
申请人： Tien-Fan Ou , Wen-Jer Tsai , Jyun-Siang Huang
发明人： Tien-Fan Ou , Wen-Jer Tsai , Jyun-Siang Huang
IPC分类号： G11C11/34
CPC分类号： G11C5/04 , G11C16/0416 , G11C16/10 , H01L27/11521 , H01L27/11568
摘要： An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell, wherein the third doped region is floating.
摘要翻译：集成电路包括包括第一单元和第二单元的存储单元结构。第一单元包括第一存储结构和衬底上的第一栅极。第一个门是第一个存储结构。第二单元包括第二存储结构和衬底上的第二栅极。第二个门是第二个存储结构。第一个门与第二个门分开。第一掺杂区域与第一单元相邻并且耦合到第一源极。第二掺杂区域被配置在衬底内且与第二单元相邻。第二掺杂区域耦合到第二源极。至少一个第三掺杂区域在第一单元和第二单元之间，其中第三掺杂区域是浮置的。

8. 发明授权

US08143665B2 Memory array and method for manufacturing and operating the same 有权
标题翻译：存储器阵列及其制造和操作方法
公开(公告)号：US08143665B2
公开(公告)日：2012-03-27
申请号：US12352947
申请日：2009-01-13
申请人： Jyun-Siang Huang , Wen-Jer Tsai , Tien-Fan Ou
发明人： Jyun-Siang Huang , Wen-Jer Tsai , Tien-Fan Ou
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/11565 , H01L29/4234 , H01L29/792
摘要： The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.
摘要翻译：本发明提供一种存储器阵列。存储器阵列包括衬底，多个字线，电荷俘获结构，多个沟槽沟道和多个位线。字线位于衬底上，字线彼此平行。电荷捕获结构覆盖每条字线的表面。沟槽沟槽位于衬底之上，并且字线和沟槽沟槽交替布置，并且通过电荷捕获结构将每个沟槽沟道与相邻字线分开。位线位于字线之上，并且每个位线跨越每一个字线，并且每个沟道沟道电耦合到位线。

9. 发明授权

US08139416B2 Operation methods for memory cell and array for reducing punch through leakage 有权
标题翻译：用于减少穿孔渗漏的存储单元和阵列的操作方法
公开(公告)号：US08139416B2
公开(公告)日：2012-03-20
申请号：US13159410
申请日：2011-06-13
申请人： Lit-Ho Chong , Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
发明人： Lit-Ho Chong , Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
IPC分类号： G11C11/34
CPC分类号： G11C5/04 , G11C16/0416 , G11C16/10 , H01L27/11521 , H01L27/11568
摘要： A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
摘要翻译：一种用于对存储器阵列中的第一存储器单元进行编程的方法。在具体实施例中，每个存储单元具有覆盖电荷存储材料和沟道的漏极，源极，沟道和控制栅极。第一存储单元的源极耦合到第二存储单元的漏极。电压施加到第一存储单元的漏极，并且第二存储单元的源极接地。该方法包括使第二存储单元的漏极和第一存储单元的源极浮置，并且导通第一和第二存储单元的通道，从而有效地形成扩展通道区域。将热载流子注入第一单元的电荷存储材料以对第一存储单元进行编程。扩展通道降低电场，并减少未选择的存储单元中的冲击。

10. 发明授权

US07995384B2 Electrically isolated gated diode nonvolatile memory 有权
标题翻译：电隔离门控二极管非易失性存储器
公开(公告)号：US07995384B2
公开(公告)日：2011-08-09
申请号：US12192797
申请日：2008-08-15
申请人： Tien-Fan Ou , Wen-Jer Tsai , Jyun-Siang Huang
发明人： Tien-Fan Ou , Wen-Jer Tsai , Jyun-Siang Huang
IPC分类号： G11C11/36
CPC分类号： H01L27/1021 , G11C11/56 , G11C16/02 , G11C17/06 , G11C2213/71 , G11C2213/72 , H01L27/11517 , H01L27/11563 , H01L29/66356 , H01L29/8616
摘要： A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子的二极管结构。相邻的存储器件是电隔离的。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式