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1. 发明申请

US20070058618A1 Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
标题翻译：用于可编程逻辑器件集成电路等的多通道通信电路
公开(公告)号：US20070058618A1
公开(公告)日：2007-03-15
申请号：US11288810
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Shumarayev , Tim Hoang , Ning Xue , Chong Lee , Ramanand Venkata
发明人： Thungoc Tran , Sergey Shumarayev , Tim Hoang , Ning Xue , Chong Lee , Ramanand Venkata
IPC分类号： H04L12/50
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作一起，八个渠道在一起等）。共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以促进诸如电路设计和验证的事情。

2. 发明授权

US07656187B2 Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
标题翻译：用于可编程逻辑器件集成电路等的多通道通信电路
公开(公告)号：US07656187B2
公开(公告)日：2010-02-02
申请号：US11288810
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang , Ning Xue , Chong Lee , Ramanand Venkata
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang , Ning Xue , Chong Lee , Ramanand Venkata
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作一起，八个渠道在一起等）。共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。

3. 发明授权

US07151470B1 Data converter with multiple conversions for padded-protocol interface 有权
标题翻译：具有多个转换的数据转换器，用于填充协议接口
公开(公告)号：US07151470B1
公开(公告)日：2006-12-19
申请号：US10969450
申请日：2004-10-20
申请人： Ning Xue , Ramanand Venkata , Chong H Lee , Rakesh Patel
发明人： Ning Xue , Ramanand Venkata , Chong H Lee , Rakesh Patel
IPC分类号： H03M7/00
CPC分类号： H03M7/04
摘要： A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.
摘要翻译：用于填充协议接口的数据转换器或“变速箱”可以执行多个不同的转换，例如在64位和66位之间，在24位和26位之间，或在48位和50位之间。这是通过使用可允许用户选择时钟速度的可编程分频器从不同时钟速度对齿轮箱进行计时的，这些时钟速度全部来自相同的主时钟（可以从接收机实施例中的数据恢复）。当转换不是设计齿轮箱的最大宽度的转换时，未使用的位将被忽略。转换器还可以在不同宽度的数据中找到用于对齐目的的填充位，当数据不是设计转换器的最宽时，再次忽略未使用的位。

4. 发明授权

US08630198B1 Apparatus and methods of dynamic transmit equalization 有权
标题翻译：动态传输均衡的装置和方法
公开(公告)号：US08630198B1
公开(公告)日：2014-01-14
申请号：US12983180
申请日：2010-12-31
申请人： Divya Vijayaraghavan , Gopi Krishnamurthy , Ning Xue , Chong H. Lee
发明人： Divya Vijayaraghavan , Gopi Krishnamurthy , Ning Xue , Chong H. Lee
IPC分类号： G01R31/08
CPC分类号： H04L25/03885 , H04B3/04 , H04B3/32 , H04L25/03343
摘要： One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及被配置为执行双向通道的动态发送均衡的集成电路。该集成电路包括物理编码和媒体访问控制电路之间的接口，以及在物理编码电路外部的配置成使用所述接口执行动态发送均衡的均衡控制电路。另一个实施例涉及一种包括物理编码电路和媒体访问控制电路的收发器电路。收发器电路还包括物理编码电路和媒体访问控制电路之间的接口以及在物理编码电路之外的均衡控制器，并且被配置为使用所述接口执行动态发送均衡。接口被配置为以时间复用的信号格式提供从媒体访问控制电路到物理编码电路的传输系数数据。还公开了其它实施例，方面和特征。

5. 发明授权

US07598767B1 Multi-standard data communication interface circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的多标准数据通信接口电路
公开(公告)号：US07598767B1
公开(公告)日：2009-10-06
申请号：US11349411
申请日：2006-02-06
申请人： Ning Xue
发明人： Ning Xue
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/17732
摘要： A programmable logic device includes a hard IP portion, which includes circuitry that is dedicated to receiving a high-speed serial data signal and performing certain basic functions related to byte alignment on that data signal, and a more general-purpose programmable logic portion. The programmable logic portion is used for such tasks as synchronizing the byte-aligned data in accordance with any one of a number of possible data communication protocols.
摘要翻译：可编程逻辑器件包括硬IP部分，其包括专用于接收高速串行数据信号并执行与该数据信号上的字节对准有关的某些基本功能的电路，以及更通用的可编程逻辑部分。可编程逻辑部分用于按照多个可能的数据通信协议中的任何一个来同步字节对齐数据的任务。

6. 发明授权

US07386767B1 Programmable bit error rate monitor for serial interface 有权
标题翻译：串行接口的可编程误码率监视器
公开(公告)号：US07386767B1
公开(公告)日：2008-06-10
申请号：US10958447
申请日：2004-10-05
申请人： Ning Xue , Chong H Lee
发明人： Ning Xue , Chong H Lee
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/076
摘要： A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.
摘要翻译：可编程误码率监视器包括错误计数器，具有可编程上限的监视周期计数器以设置监视周期，以及将实际错误计数与可编程阈值进行比较的错误标志发生器。错误标志生成器可以生成不同灵敏度级别的标志，并且用户可以可编程地选择这些标志之一。这三个标志可以由独立的比较器产生，或者它们可以从基本错误标志中外推，例如通过仅将错误计数的某些位与阈值的相应位进行比较。

7. 发明申请

US20070288298A1 System and method for behaviorally targeting electronic communications 审中-公开
标题翻译：针对电子通信的行为定位系统和方法
公开(公告)号：US20070288298A1
公开(公告)日：2007-12-13
申请号：US11449306
申请日：2006-06-08
申请人： Chris Gutierrez , Ning Xue
发明人： Chris Gutierrez , Ning Xue
IPC分类号： G06F17/30
CPC分类号： G06Q30/02 , G06Q30/0201
摘要： Methods and systems for determining the correlation between electronic informational campaigns, for example, two advertising campaigns by a two phase process, based on the behavior of multiple users. In a first phase, probabilities of one campaign, with respect to another campaign, are calculated, and values of expected revenue for each campaign are determined from the probabilities. The campaigns with the greatest expected revenues are then analyzed, to determine the extent of their correlation, in the second phase. In the second phase, the correlation between two campaigns is determined, by determining a correlation value, indicative of the correlation between two campaigns.
摘要翻译：基于多个用户的行为来确定电子信息活动之间的相关性的方法和系统，例如两阶段过程的两个广告活动。在第一阶段，计算一个广告系列的概率，并针对另一个广告系列计算出每个广告系列的预期收入的价值，从概率确定。然后分析具有最大预期收入的运动，以确定其相关性的程度，在第二阶段。在第二阶段，通过确定表示两个活动之间的相关性的相关值来确定两个活动之间的相关性。

8. 发明授权

US07199732B1 Data converter with reduced component count for padded-protocol interface 有权
标题翻译：数据转换器，减少了填充协议接口的组件数量
公开(公告)号：US07199732B1
公开(公告)日：2007-04-03
申请号：US11139083
申请日：2005-05-26
申请人： Ning Xue , Chong H Lee
发明人： Ning Xue , Chong H Lee
IPC分类号： H03M7/00
CPC分类号： H04L25/4908
摘要： A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).
摘要翻译：用于填充协议接口的数据转换器或“变速箱”通过处理较窄的中间数据流来减少数量的组件，同时将其中间输入和输出的时钟速度乘以使其处理更多的数据时钟周期。数据流可以缩小为原始宽度（原始宽度除外）的任何整数因子。

9. 发明授权

US08833737B2 Rackable fencing of components optimized for preassembly shipping 有权
标题翻译：组装运输优化组件的可拆卸围栏
公开(公告)号：US08833737B2
公开(公告)日：2014-09-16
申请号：US13351927
申请日：2012-01-17
申请人： Duane E. Langenwalter , Ning Xue
发明人： Duane E. Langenwalter , Ning Xue
IPC分类号： E04H17/14
CPC分类号： E04H17/1426
摘要： A rackable fence with a rail, picket carrier, and plurality of pickets. The rail defines a rigid inverted U-shaped cross-section. The picket carrier includes a top span residing within and extending across the interior of the rail. The pickets are pivotally attached to the picket carrier and pivotable toward the rail.
摘要翻译：带有轨道，支架托架和多个支架的可机架围栏。导轨限定了刚性的倒U形横截面。支架载体包括位于轨道内部并延伸穿过轨道内部的顶部跨距。支杆可枢转地附接到支架托架并且能够朝向轨道枢转。

10. 发明授权

US08363770B1 Oversampling with programmable pointer adjustment 有权
标题翻译：可编程指针调整过采样
公开(公告)号：US08363770B1
公开(公告)日：2013-01-29
申请号：US11555570
申请日：2006-11-01
申请人： Ning Xue , Chong H. Lee
发明人： Ning Xue , Chong H. Lee
IPC分类号： H04L12/50
CPC分类号： H04L7/0338 , H04L7/0331
摘要： Systems, methods, and circuits extract data from an oversampled data stream in the presence of noise and/or jitter. Pointers decide which data samples of the oversampled data stream are extracted. Some of the pointers occurring right after a data transition are positioned based on the location of previous pointers, rather than using the data transition points as occurs during an alignment. Settings such as the frequency of how often a pointer is aligned with a data transition and a maximum adjustment amount during an alignment may be programmable.
摘要翻译：系统，方法和电路在存在噪声和/或抖动的情况下从过采样数据流中提取数据。指针决定提取过采样数据流的哪些数据样本。在数据转换之后发生的一些指针基于先前指针的位置而定位，而不是使用在对齐期间发生的数据转换点。诸如指针与数据转换对齐频率的频率以及在对准期间的最大调整量的设置可以是可编程的。

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