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1. 发明授权

US08053273B2 Shallow PN junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process 有权
标题翻译：通过循环生长/蚀刻沉积工艺在嵌入式半导体合金的选择性生长期间通过原位掺杂形成浅的PN结
公开(公告)号：US08053273B2
公开(公告)日：2011-11-08
申请号：US12504758
申请日：2009-07-17
申请人： Thorsten Kammler , Andy Wei , Ina Ostermay
发明人： Thorsten Kammler , Andy Wei , Ina Ostermay
IPC分类号： H01L21/00
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
摘要翻译：可以在漏极和源极区域中形成硅/碳合金，其中另一部分可以作为相对于栅电极材料的偏移减小的原位掺杂材料提供。为此，在一个说明性实施例中，可以在超高真空环境中的低温下使用包括多个生长/蚀刻循环的循环外延生长工艺，从而获得基本上从底部到顶部的填充行为。

2. 发明授权

US08906811B2 Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process 有权
标题翻译：通过在循环生长/蚀刻沉积工艺中嵌入式半导体合金的选择性生长期间通过原位掺杂形成浅的pn结
公开(公告)号：US08906811B2
公开(公告)日：2014-12-09
申请号：US13272672
申请日：2011-10-13
申请人： Thorsten Kammler , Andy Wei , Ina Ostermay
发明人： Thorsten Kammler , Andy Wei , Ina Ostermay
IPC分类号： H01L21/302 , H01L21/461 , H01L29/10 , H01L29/78 , H01L29/66 , H01L21/265
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
摘要翻译：可以在漏极和源极区域中形成硅/碳合金，其中另一部分可以作为相对于栅电极材料的偏移减小的原位掺杂材料提供。为此，在一个说明性实施例中，可以在超高真空环境中的低温下使用包括多个生长/蚀刻循环的循环外延生长工艺，从而获得基本上从底部到顶部的填充行为。

3. 发明申请

US20120032278A1 SHALLOW PN JUNCTION FORMED BY IN SITU DOPING DURING SELECTIVE GROWTH OF AN EMBEDDED SEMICONDUCTOR ALLOY BY A CYCLIC GROWTH/ETCH DEPOSITION PROCESS 有权
标题翻译：通过循环生长/蚀刻沉积过程在嵌入式半导体合金的选择性生长期间由现场掺杂形成的PN结
公开(公告)号：US20120032278A1
公开(公告)日：2012-02-09
申请号：US13272672
申请日：2011-10-13
申请人： Thorsten Kammler , Andy Wei , Ina Ostermay
发明人： Thorsten Kammler , Andy Wei , Ina Ostermay
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
摘要翻译：可以在漏极和源极区域中形成硅/碳合金，其中另一部分可以作为相对于栅电极材料的偏移减小的原位掺杂材料提供。为此，在一个说明性实施例中，可以在超高真空环境中的低温下使用包括多个生长/蚀刻循环的循环外延生长工艺，从而获得基本上从底部到顶部的填充行为。

4. 发明申请

US20100025779A1 SHALLOW PN JUNCTION FORMED BY IN SITU DOPING DURING SELECTIVE GROWTH OF AN EMBEDDED SEMICONDUCTOR ALLOY BY A CYCLIC GROWTH/ETCH DEPOSITION PROCESS 有权
标题翻译：通过循环生长/蚀刻沉积过程在嵌入式半导体合金的选择性生长期间由现场掺杂形成的PN结
公开(公告)号：US20100025779A1
公开(公告)日：2010-02-04
申请号：US12504758
申请日：2009-07-17
申请人： Thorsten Kammler , Andy Wei , Ina Ostermay
发明人： Thorsten Kammler , Andy Wei , Ina Ostermay
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.
摘要翻译：可以在漏极和源极区域中形成硅/碳合金，其中另一部分可以作为相对于栅电极材料的偏移减小的原位掺杂材料提供。为此，在一个说明性实施例中，可以在超高真空环境中的低温下使用包括多个生长/蚀刻循环的循环外延生长工艺，从而获得基本上从底部到顶部的填充行为。

5. 发明申请

US20130029463A1 Methods of Forming a PMOS Device with In Situ Doped Epitaxial Source/Drain Regions 有权
标题翻译：用原位掺杂的外延源/漏区形成PMOS器件的方法
公开(公告)号：US20130029463A1
公开(公告)日：2013-01-31
申请号：US13190940
申请日：2011-07-26
申请人： Ralf Illgen , Stefan Flachowsky , Ina Ostermay
发明人： Ralf Illgen , Stefan Flachowsky , Ina Ostermay
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括分别在用于PMOS器件和NMOS器件的PMOS区域和半导体衬底的NMOS区域中形成扩展注入区域，并且在形成扩展注入区域之后，执行第一加热过程。该方法还包括在衬底的PMOS区域中形成多个空腔，执行至少一个外延沉积工艺以形成位于每个所述空腔中或上方的多个原位掺杂半导体层，并形成掩模暴露NMOS区并覆盖PMOS区的层。该方法的结论是在用于NMOS器件的衬底的NMOS区域中形成源极/漏极注入区域并执行第二加热过程的步骤。

6. 发明申请

US20130069123A1 CMOS SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS 审中-公开
标题翻译：具有压力区域的CMOS半导体器件及相关制造方法
公开(公告)号：US20130069123A1
公开(公告)日：2013-03-21
申请号：US13235173
申请日：2011-09-16
申请人： Ralf Illgen , Stefan Flachowsky , Ina Ostermay
发明人： Ralf Illgen , Stefan Flachowsky , Ina Ostermay
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L21/823814 , H01L21/26586 , H01L21/823807 , H01L29/165 , H01L29/66492 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming first doped stressor regions in a first region of semiconductor material, forming second doped stressor regions in a second region of semiconductor material after forming the first doped stressor regions, and after forming the second doped stressor regions, annealing the semiconductor device structure to activate ions of the first and second doped stressor regions concurrently. The amount of time for the annealing is chosen to inhibit diffusion of the ions of the first and second doped stressor regions.
摘要翻译：提供了半导体器件和相关的制造方法。示例性制造方法包括在半导体材料的第一区域中形成第一掺杂应力区域，在形成第一掺杂应力区域之后在半导体材料的第二区域中形成第二掺杂应力区域，并且在形成第二掺杂应力区域之后，对半导体器件结构，以同时激活第一和第二掺杂应力区的离子。选择退火的时间量以抑制第一和第二掺杂应力区域的离子的扩散。

7. 发明授权

US08466018B2 Methods of forming a PMOS device with in situ doped epitaxial source/drain regions 有权
标题翻译：用原位掺杂的外延源/漏区形成PMOS器件的方法
公开(公告)号：US08466018B2
公开(公告)日：2013-06-18
申请号：US13190940
申请日：2011-07-26
申请人： Ralf Illgen , Stefan Flachowsky , Ina Ostermay
发明人： Ralf Illgen , Stefan Flachowsky , Ina Ostermay
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L21/823814 , H01L21/823807
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括分别在用于PMOS器件和NMOS器件的PMOS区域和半导体衬底的NMOS区域中形成扩展注入区域，并且在形成扩展注入区域之后，执行第一加热过程。该方法还包括在衬底的PMOS区域中形成多个空腔，执行至少一个外延沉积工艺以形成位于每个所述空腔中或上方的多个原位掺杂半导体层，并形成掩模暴露NMOS区并覆盖PMOS区的层。该方法的结论是在用于NMOS器件的衬底的NMOS区域中形成源极/漏极注入区域并执行第二加热过程的步骤。

8. 发明授权

US08728896B2 Embedded sigma-shaped semiconductor alloys formed in transistors by applying a uniform oxide layer prior to cavity etching 有权
标题翻译：通过在腔蚀刻之前施加均匀的氧化物层，形成在晶体管中的嵌入式σ形半导体合金
公开(公告)号：US08728896B2
公开(公告)日：2014-05-20
申请号：US13238180
申请日：2011-09-21
申请人： Stephan Kronholz , Andreas Ott , Ina Ostermay
发明人： Stephan Kronholz , Andreas Ott , Ina Ostermay
IPC分类号： H01L21/66 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L22/12
摘要： When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime.
摘要翻译：当形成需要嵌入式半导体合金的复杂晶体管时，可以通过提供均匀的氧化物层来在例如晶体学各向异性蚀刻步骤的基础上形成具有优异均匀性的空腔，以便减少与工艺相关的波动或排队时间变化。可以基于APC控制方式形成均匀的氧化物层。

9. 发明申请

US20120161249A1 Reduction of Defect Rates in PFET Transistors Comprising a Silicon/Germanium Semiconductor Material by Providing a Graded Germanium Concentration 审中-公开
标题翻译：通过提供分级锗浓度来减少包含硅/锗半导体材料的PFET晶体管中的缺陷率
公开(公告)号：US20120161249A1
公开(公告)日：2012-06-28
申请号：US13338349
申请日：2011-12-28
申请人： Stephan-Detlef Kronholz , Ina Ostermay , Roman Boschke
发明人： Stephan-Detlef Kronholz , Ina Ostermay , Roman Boschke
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： When forming sophisticated gate electrode structures in an early manufacturing stage, the threshold voltage characteristics may be adjusted on the basis of a semiconductor alloy, which may be formed on the basis of low pressure CVD techniques. In order to obtain a desired high band gap offset, for instance with respect to a silicon/germanium alloy, a moderately high germanium concentration may be provided within the semiconductor alloy, wherein, however, at the interface formed with the semiconductor base material, a low germanium concentration may significantly reduce the probability of creating dislocation defects.
摘要翻译：当在早期制造阶段形成复杂的栅电极结构时，可以基于可以基于低压CVD技术形成的半导体合金来调整阈值电压特性。为了获得期望的高带隙偏移，例如对于硅/锗合金，可以在半导体合金内提供适度高的锗浓度，然而，在与半导体基底材料形成的界面处，低锗浓度可能会显着降低产生位错缺陷的可能性。

10. 发明申请

US20120153402A1 EMBEDDED SIGMA-SHAPED SEMICONDUCTOR ALLOYS FORMED IN TRANSISTORS BY APPLYING A UNIFORM OXIDE LAYER PRIOR TO CAVITY ETCHING 有权
标题翻译：通过在空洞蚀刻前应用均匀的氧化物层在晶体管中形成的嵌入式SIGMA-形状的半导体合金
公开(公告)号：US20120153402A1
公开(公告)日：2012-06-21
申请号：US13238180
申请日：2011-09-21
申请人： Stephan Kronholz , Andreas Ott , Ina Ostermay
发明人： Stephan Kronholz , Andreas Ott , Ina Ostermay
IPC分类号： H01L27/088 , H01L21/66
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L22/12
摘要： When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime.
摘要翻译：当形成需要嵌入式半导体合金的复杂晶体管时，可以通过提供均匀的氧化物层来在例如晶体学各向异性蚀刻步骤的基础上形成具有优异均匀性的空腔，以便减少与工艺相关的波动或排队时间变化。可以基于APC控制方式形成均匀的氧化物层。

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