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1. 发明授权

US06859885B2 Data reception method 失效
标题翻译：数据接收方式
公开(公告)号：US06859885B2
公开(公告)日：2005-02-22
申请号：US10000386
申请日：2001-11-30
申请人： Thomas Wagner , Eberhard Boehl , Andrej Morosov
发明人： Thomas Wagner , Eberhard Boehl , Andrej Morosov
IPC分类号： H04L1/00 , H04L7/00 , H04L7/033 , H04L7/04 , H04L7/08 , H04J3/06
CPC分类号： H04L7/0338 , H04L7/033 , H04L7/048 , H04L7/08
摘要： A data reception method is described in which errors due to a phase shift between the data signals and the clock pulse are compensated in data signals transmitted at a constant frequency with the receiving device operating at this frequency by operating two readout devices with a time offset, and a signal output by one of the readout devices is selected, after which this signal is checked for validity. This makes additional transmission of an operating clock pulse via a bus system and synchronization of an input signal with an operating clock unnecessary.
摘要翻译：描述了一种数据接收方法，其中通过操作具有时间偏移的两个读出装置，以接收装置以该频率工作的数据信号以恒定频率发送的数据信号和时钟脉冲之间的相移导致的误差被补偿，并且选择由读出装置中的一个输出的信号，之后检查该信号的有效性。这使得经由总线系统的操作时钟脉冲的附加传输和输入信号与工作时钟的同步是不必要的。

2. 发明授权

US09342096B2 Modular structure for processing data 有权
标题翻译：用于处理数据的模块化结构
公开(公告)号：US09342096B2
公开(公告)日：2016-05-17
申请号：US13637061
申请日：2011-03-16
申请人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
发明人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
IPC分类号： G06F1/12 , G06F1/10 , G06F1/14
CPC分类号： G06F1/10 , G06F1/14
摘要： A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.
摘要翻译：用于数据处理系统的电路装置被配置为处理多个模块中的数据。电路布置被配置为使得每个模块被提供有至少一个时钟脉冲，时基和至少一个附加物理变量的基极。电路装置还包括中央路由单元，多个模块耦合到该中央路由单元，多个模块可以经由该中央路由单元基于时基和/或其他物理变量的基础周期性地在它们之间交换数据。每个模块独立配置并且与多个模块中的其他模块并行配置，以便处理数据。电路装置采用相应的方法。

3. 发明申请

US20130227331A1 Modular Structure for Processing Data 有权
标题翻译：处理数据的模块化结构
公开(公告)号：US20130227331A1
公开(公告)日：2013-08-29
申请号：US13637061
申请日：2011-03-16
申请人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
发明人： Eberhard Boehl , Ruben Bartholomae , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Axel Aue , Dieter Thoss , Thomas Lindenkreuz , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Bernd Becker
IPC分类号： G06F1/10
CPC分类号： G06F1/10 , G06F1/14
摘要： A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.
摘要翻译：用于数据处理系统的电路装置被配置为处理多个模块中的数据。电路布置被配置为使得每个模块被提供有至少一个时钟脉冲，时基和至少一个附加物理变量的基极。电路装置还包括中央路由单元，多个模块耦合到该中央路由单元，多个模块可以经由该中央路由单元基于时基和/或其他物理变量的基础周期性地在它们之间交换数据。每个模块独立配置并且与多个模块中的其他模块并行配置，以便处理数据。电路装置采用相应的方法。

4. 发明申请

US20130111189A1 Circuit Arrangement for a Data Processing System and Method for Data Processing 有权
标题翻译：数据处理系统的电路布置和数据处理方法
公开(公告)号：US20130111189A1
公开(公告)日：2013-05-02
申请号：US13638125
申请日：2011-03-18
申请人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
IPC分类号： G06F15/76
CPC分类号： G06F15/76 , G06F1/04
摘要： A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.
摘要翻译：用于数据处理系统的电路装置被配置为处理多个模块中的数据。电路布置被配置为为多个模块中的每一个提供时钟以及时基和/或至少一个另外的物理量的基极。电路装置还包括中央路由单元，其连接到多个模块中的若干个。通过中央路由单元，模块可以基于时基和/或基于至少一个其他物理量周期性地交换数据。多个模块被配置为独立于和并行地处理数个模块的其他模块的数据。

5. 发明授权

US09367516B2 Circuit arrangement for a data processing system and method for data processing 有权
标题翻译：数据处理系统的电路布置和数据处理方法
公开(公告)号：US09367516B2
公开(公告)日：2016-06-14
申请号：US13638125
申请日：2011-03-18
申请人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Ruben Bartholomae , Matthias Knauss , Stephen Schmitt , Thomas Wagner , Andreas Hempel , Dieter Thoss , Bernhard Mader , Achim Schaefer , Juergen Hanisch , Uwe Scheurer , Andreas Merker , Rolf Kurrer , Bernd Becker , Bernard Pawlok
IPC分类号： G06F1/12 , G06F15/76 , G06F1/04
CPC分类号： G06F15/76 , G06F1/04
摘要： A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.
摘要翻译：用于数据处理系统的电路装置被配置为处理多个模块中的数据。电路布置被配置为为多个模块中的每一个提供时钟以及时基和/或至少一个另外的物理量的基极。电路装置还包括中央路由单元，其连接到多个模块中的若干个。通过中央路由单元，模块可以基于时基和/或基于至少一个其他物理量周期性地交换数据。多个模块被配置为独立于和并行地处理数个模块的其他模块的数据。

6. 发明授权

US09184679B2 Method for predicting the duration of a future time interval 有权
标题翻译：预测未来时间间隔持续时间的方法
公开(公告)号：US09184679B2
公开(公告)日：2015-11-10
申请号：US13577475
申请日：2011-01-12
申请人： Eberhard Boehl , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Bernd Becker , Bernard Pawlok
IPC分类号： G06F7/00 , H02P6/00 , F02D41/00
CPC分类号： H02P6/34 , F02D41/009 , F02D41/0097
摘要： A method for predicting a value for a length of a future time interval in which a physical variable changes is described, in which at least one measured value for the length of a past time interval and an instantaneously measured value for a length of an instantaneous time interval are taken into account, m values for lengths of past time intervals being added. A first value precedes the instantaneously measured value by k−1, and an mth value precedes the instantaneously measured value by k−m. The m added values are divided by a value for a length of a past time interval which precedes the instantaneously measured value by k. A ratio of the mentioned values is formed. For determining the value to be predicted, an average error is initially added to the instantaneously measured value, forming a sum. The formed ratio is subsequently applied to this sum.
摘要翻译：描述用于预测物理变量改变的未来时间间隔的长度的值的方法，其中对于过去时间间隔的长度的至少一个测量值和瞬时时间的长度的瞬时测量值考虑间隔时间，添加过去时间间隔的长度的m值。第一个值先于瞬时测量值k-1，第m个值先于瞬时测量值k-m。将m个附加值除以在瞬时测量值之前的过去时间间隔的长度的值。形成上述值的比例。为了确定要预测的值，首先将平均误差加到瞬时测量值上，形成一个和。形成的比率随后应用于这个总和。

7. 发明申请

US20130096872A1 CIRCUIT ARRANGEMENT AND METHOD FOR EVALUATING SIGNALS OF A CRANKSHAFT SENSOR AND OF A CAMSHAFT SENSOR OF AN INTERNAL COMBUSTION ENGINE 有权
标题翻译：用于评估起重机传感器和内燃机的CAMSHAFT传感器的信号的电路布置和方法
公开(公告)号：US20130096872A1
公开(公告)日：2013-04-18
申请号：US13637170
申请日：2011-03-31
申请人： Eberhard Boehl
发明人： Eberhard Boehl
IPC分类号： G06F17/18
CPC分类号： G06F17/18 , F02D41/009 , F02D41/222 , Y02T10/40
摘要： A circuit assemblage and a method for evaluating signals of a crankshaft sensor and of a camshaft sensor of an internal combustion engine are provided, the times at which the signals occur being evaluated. A position signal of a shaft of the internal combustion engine is formed from the times. Storage units are provided which simultaneously store the occurrence times of the signals of the crankshaft sensor and the occurrence times of signals of the camshaft sensor. A decision unit is provided as to whether the position signal is formed from the occurrence times of the signals of the crankshaft sensor or from the occurrence times of the signals of the camshaft sensor.
摘要翻译：提供了用于评估曲轴传感器和内燃机的凸轮轴传感器的信号的电路组合和方法，评估发生信号的时间。内燃机的轴的位置信号由时间形成。提供存储单元，其同时存储曲轴传感器的信号的发生时间和凸轮轴传感器的信号的发生时间。根据曲轴传感器的信号的发生时间或凸轮轴传感器的信号的出现次数，提供位置信号是否形成决定单元。

8. 发明申请

US20130082693A1 Device and method for processing signals which represent an angular position of a motor shaft 有权
标题翻译：用于处理表示电动机轴的角位置的信号的装置和方法
公开(公告)号：US20130082693A1
公开(公告)日：2013-04-04
申请号：US13637106
申请日：2011-03-31
申请人： Eberhard Boehl
发明人： Eberhard Boehl
IPC分类号： G01B7/30
CPC分类号： G01B7/30 , G01D5/2451
摘要： In an apparatus and a method for processing signals that represent an angular position of a shaft of a motor, a storage unit for storing arrival times of the signals in a memory is provided, the storage unit additionally evaluating a rotation direction datum of the shaft. Storage of the times in the memory is performed in a first sequence in the event of a rotation of the shaft in a first direction, and storage in the memory is performed in a second sequence that is opposite to the first sequence in the event of a rotation of the shaft in a second direction that is opposite to the first direction.
摘要翻译：在用于处理表示电动机的轴的角位置的信号的装置和方法中，提供了用于将信号到达时间存储在存储器中的存储单元，该存储单元另外评估轴的旋转方向基准。在轴的第一方向旋转的情况下，以第一顺序执行存储器中的时间的存储，并且在存储器中的存储器中的存储器以与第一序列相反的第二序列执行轴在与第一方向相反的第二方向上的旋转。

9. 发明申请

US20130079897A1 TIMER MODULE AND METHOD FOR CHECKING AN OUTPUT SIGNAL 有权
标题翻译：定时器模块和检查输出信号的方法
公开(公告)号：US20130079897A1
公开(公告)日：2013-03-28
申请号：US13637142
申请日：2011-03-16
申请人： Eberhard Boehl , Ruben Bartholomae
发明人： Eberhard Boehl , Ruben Bartholomae
IPC分类号： G05B11/01
CPC分类号： G05B19/0425 , B60W50/04 , G05B2219/21166 , G05B2219/25278
摘要： A method for checking an output signal of a timer module is provided, the timer module having at least one output module, at least one input module, and at least one logic module. The output signal to be checked is read in into the timer module via an input module in addition to its output via an output module, and in the input module, signal characteristics to be checked are determined for the output signal to be checked. Furthermore, the signal characteristics to be checked are read by the logic module from the input module and the signal characteristics to be checked are compared in the logic module to the predefined values for the signal characteristics.
摘要翻译：提供了一种用于检查定时器模块的输出信号的方法，所述定时器模块具有至少一个输出模块，至少一个输入模块和至少一个逻辑模块。要检查的输出信号除了通过输出模块的输出外，还经由输入模块读入定时器模块，并且在输入模块中，确定要检查的输出信号的要检查的信号特性。此外，逻辑模块从输入模块读取要检查的信号特性，并将要检查的信号特性在逻辑模块中与信号特性的预定义值进行比较。

10. 发明申请

US20130077733A1 Circuit Configuration And Method For Distributing Pulses Within A Time Interval 有权
标题翻译：在一段时间内分配脉冲的电路配置和方法
公开(公告)号：US20130077733A1
公开(公告)日：2013-03-28
申请号：US13637159
申请日：2011-03-16
申请人： Eberhard Boehl , Bernard Pawlok
发明人： Eberhard Boehl , Bernard Pawlok
IPC分类号： H03K21/00
CPC分类号： H03K21/00 , G06F7/68
摘要： A circuit configuration for generating pulses within a time interval on the basis of an input signal includes a counting unit, a comparator unit and a first adder circuit; the time interval being predicted on the basis of at least two defined changes in input signals; the circuit configuration being configured for triggering at the beginning of the time interval by the first adder circuit on the basis of clock pulses, for generating and outputting pulses; for counting a number of generated and output pulses using the counting unit;for comparing the counted number to a setpoint value using the comparator unit; and for ending the generation and outputting of the pulses in response to the reaching of the setpoint value or the ending of the time interval.
摘要翻译：基于输入信号在时间间隔内产生脉冲的电路结构包括计数单元，比较器单元和第一加法器电路; 基于输入信号中至少两个确定的变化来预测的时间间隔; 所述电路配置被配置为基于时钟脉冲在所述时间间隔开始时由所述第一加法器电路触发，用于产生和输出脉冲; 用于使用所述计数单元计数多个产生和输出脉冲; 用于使用比较器单元将计数的数量与设定值进行比较; 并且响应于达到设定值或结束时间间隔而结束脉冲的产生和输出。

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