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1. 发明申请

US20090234777A1 METHODS, APPARATUS, AND PROGRAM PRODUCTS TO OPTIMIZE SEMICONDUCTOR PRODUCT YIELD PREDICTION FOR PERFORMANCE AND LEAKAGE SCREENS 有权
标题翻译：方法，装置和程序产品优化半导体产品的性能和漏电屏幕预测
公开(公告)号：US20090234777A1
公开(公告)日：2009-09-17
申请号：US12046237
申请日：2008-03-11
申请人： Thomas S. Barnett , Jeanne Paulette Spence Bickford , Nazmul Habib , Susan K. Lichtensteiger , Raymond J. Rosner
发明人： Thomas S. Barnett , Jeanne Paulette Spence Bickford , Nazmul Habib , Susan K. Lichtensteiger , Raymond J. Rosner
IPC分类号： G06Q10/00 , G06G7/48 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5045 , G06F2217/14 , G06Q30/0283 , H01L22/20
摘要： An apparatus, method, and program product are provided to predict yield loss associated with performance screens or leakage screens. A leakage model is correlated to an on-chip measurement. Current limited yields are determined from the leakage model. A database is formed relating performance sigma cut-points to the circuit limited yields. A product is quoted based on the circuit limited yield for one of the performance sigma cut-points taken from the database. The quote is tied to the product design and testing.
摘要翻译：提供了一种装置，方法和程序产品来预测与性能屏幕或泄漏屏幕相关联的屈服损失。泄漏模型与片上测量相关。目前有限的产量是根据泄漏模型确定的。形成一个关于性能西格玛切割点与电路有限产量的数据库。基于从数据库中获取的性能西格玛切割点之一的电路限制产量引用了产品。报价与产品设计和测试有关。

2. 发明授权

US07917451B2 Methods, apparatus, and program products to optimize semiconductor product yield prediction for performance and leakage screens 有权
标题翻译：方法，设备和程序产品，以优化性能和泄漏屏幕的半导体产品产量预测
公开(公告)号：US07917451B2
公开(公告)日：2011-03-29
申请号：US12046237
申请日：2008-03-11
申请人： Thomas S. Barnett , Jeanne Paulette Spence Bickford , Nazmul Habib , Susan K. Lichtensteiger , Raymond J. Rosner
发明人： Thomas S. Barnett , Jeanne Paulette Spence Bickford , Nazmul Habib , Susan K. Lichtensteiger , Raymond J. Rosner
IPC分类号： G06F17/00
CPC分类号： G06F17/5036 , G06F17/5045 , G06F2217/14 , G06Q30/0283 , H01L22/20
摘要： An apparatus, method, and program product are provided to predict yield loss associated with performance screens or leakage screens. A leakage model is correlated to an on-chip measurement. Current limited yields are determined from the leakage model. A database is formed relating performance sigma cut-points to the circuit limited yields. A product is quoted based on the circuit limited yield for one of the performance sigma cut-points taken from the database. The quote is tied to the product design and testing.
摘要翻译：提供了一种装置，方法和程序产品来预测与性能屏幕或泄漏屏幕相关联的屈服损失。泄漏模型与片上测量相关。目前有限的产量是根据泄漏模型确定的。形成一个关于性能西格玛切割点与电路有限产量的数据库。基于从数据库中获取的性能西格玛切割点之一的电路限制产量引用了产品。报价与产品设计和测试有关。

3. 发明授权

US10067184B2 Product performance test binning 有权
公开(公告)号：US10067184B2
公开(公告)日：2018-09-04
申请号：US13294243
申请日：2011-11-11
申请人： Theodoros Anemikos , Jeanne Bickford , Nazmul Habib , Susan K. Lichtensteiger
发明人： Theodoros Anemikos , Jeanne Bickford , Nazmul Habib , Susan K. Lichtensteiger
IPC分类号： G01R27/28 , G01R31/00 , G01R31/14 , G01R31/317
摘要： A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of a set of voltages bins corresponding to frequency specification limits of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.

4. 发明申请

US20090295402A1 VOLTAGE ISLAND PERFORMANCE/LEAKAGE SCREEN MONITOR FOR IP CHARACTERIZATION 有权
标题翻译：电压岛性能/泄漏屏幕监控用于IP特性
公开(公告)号：US20090295402A1
公开(公告)日：2009-12-03
申请号：US12131476
申请日：2008-06-02
申请人： Bruce Balch , Nazmul Habib , Susan K. Lichtensteiger , Daniel L. Stasiak , Richard A. Wachnik
发明人： Bruce Balch , Nazmul Habib , Susan K. Lichtensteiger , Daniel L. Stasiak , Richard A. Wachnik
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.
摘要翻译：提供了一种表征具有至少一个电压岛和至少一个性能屏幕环形振荡器（PSRO）的芯片的性能的方法。片上性能监视器（OCPM）被并入电压岛。电压岛的性能测量仅在电源岛上产生。性能屏幕环形振荡器（PSRO）的性能测量仅在电源电压岛下产生。将性能屏幕环形振荡器（PSRO）的性能测量与片内性能监视器（OCPM）的性能测量进行比较，以确定由于电压岛引起的系统偏移。使用由于电压岛引起的系统偏移来调整性能模型。

5. 发明申请

US20130113514A1 SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL 有权
标题翻译：用于动态和自适应功率控制的速度波动
公开(公告)号：US20130113514A1
公开(公告)日：2013-05-09
申请号：US13288269
申请日：2011-11-03
申请人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
发明人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
IPC分类号： H03K19/00 , G06F17/50
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非易失性存储介质存储电压仓的边界作为速度分级测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

6. 发明授权

US08421495B1 Speed binning for dynamic and adaptive power control 有权
标题翻译：用于动态和自适应功率控制的速度分组
公开(公告)号：US08421495B1
公开(公告)日：2013-04-16
申请号：US13288269
申请日：2011-11-03
申请人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
发明人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
IPC分类号： H03K19/003
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非易失性存储介质存储电压仓的边界作为速度分级测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

7. 发明授权

US08020138B2 Voltage island performance/leakage screen monitor for IP characterization 有权
标题翻译：电压岛性能/泄漏屏幕监视器用于IP表征
公开(公告)号：US08020138B2
公开(公告)日：2011-09-13
申请号：US12131476
申请日：2008-06-02
申请人： Bruce Balch , Nazmul Habib , Susan K. Lichtensteiger , Daniel L. Stasiak , Richard A. Wachnik
发明人： Bruce Balch , Nazmul Habib , Susan K. Lichtensteiger , Daniel L. Stasiak , Richard A. Wachnik
IPC分类号： G06F17/50
CPC分类号： G01R31/2884
摘要： A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island.
摘要翻译：提供了一种表征具有至少一个电压岛和至少一个性能屏幕环形振荡器（PSRO）的芯片的性能的方法。片上性能监视器（OCPM）被并入电压岛。电压岛的性能测量仅在电源岛上产生。性能屏幕环形振荡器（PSRO）的性能测量仅在电源电压岛下产生。将性能屏幕环形振荡器（PSRO）的性能测量与片内性能监视器（OCPM）的性能测量进行比较，以确定由于电压岛引起的系统偏移。使用由于电压岛引起的系统偏移来调整性能模型。

8. 发明申请

US20130124133A1 PRODUCT PERFORMANCE TEST BINNING 审中-公开
标题翻译：产品性能测试
公开(公告)号：US20130124133A1
公开(公告)日：2013-05-16
申请号：US13294243
申请日：2011-11-11
申请人： Theodoros Anemikos , Jeanne Bickford , Nazmul Habib , Susan K. Lichtensteiger
发明人： Theodoros Anemikos , Jeanne Bickford , Nazmul Habib , Susan K. Lichtensteiger
IPC分类号： G06F19/00
CPC分类号： G01R31/31718
摘要： A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.
摘要翻译：一种用于电压组合集成电路芯片的方法，测试系统和计算机程序产品和系统。该方法包括使用集成电路芯片的数据路径的功能测试来选择或改变集成电路芯片的电压仓。

9. 发明申请

US20130326459A1 POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL 有权
标题翻译：功率/性能优化通过温度/电压控制
公开(公告)号：US20130326459A1
公开(公告)日：2013-12-05
申请号：US13749851
申请日：2013-01-25
申请人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
发明人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31721 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.
摘要翻译：一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度切点实现了平均功耗目标。接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。

10. 发明申请

US20090228843A1 METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT 失效
标题翻译：通过调节选择性电压激活切割点来优化功率的方法
公开(公告)号：US20090228843A1
公开(公告)日：2009-09-10
申请号：US12041729
申请日：2008-03-04
申请人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.
摘要翻译：在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路和相对较快的集成电路器件。该方法选择初始操作速度切割点以使相对较慢的集成电路和相对快速的集成电路器件的最大功率电平最小化。然后，该方法使用集成电路设计制造集成电路器件，并测试集成电路器件的工作速度和功耗水平。然后，该方法基于测试将初始切割点调整到最终切割点，以使相对较慢的集成电路和相对较快的集成电路器件的最大功率电平最小化。

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