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1. 发明授权

US08824967B2 Dynamically changing a transmitter sampling frequency for a digital-to-analog converter (DAC) to reduce interference from DAC images 有权
标题翻译：动态更改数模转换器（DAC）的发射机采样频率，以减少DAC图像的干扰
公开(公告)号：US08824967B2
公开(公告)日：2014-09-02
申请号：US12823668
申请日：2010-06-25
申请人： Thomas D. Marra , Soon-Seng Lau , Inyup Kang , Arash Mirbagheri
发明人： Thomas D. Marra , Soon-Seng Lau , Inyup Kang , Arash Mirbagheri
IPC分类号： H04B1/00 , H04B1/52 , H04B1/04 , H03M1/66
CPC分类号： H04B1/525 , H03M1/661 , H04B1/0475
摘要： A method for interference reduction is described. The method is implemented in a wireless device. It is determined that a page is going to be received via a secondary receiver. It is also determined that a digital-to-analog converter (DAC) image from a transmitter will cause interference with the secondary receiver when the page is received. A sampling frequency of the DAC for the transmitter is changed so that there are not any DAC images from the transmitter that will cause interference with the secondary receiver.
摘要翻译：描述了一种减少干扰的方法。该方法在无线设备中实现。确定将通过次级接收器接收页面。还确定，当接收到页面时，来自发射器的数模转换器（DAC）图像将引起与次级接收机的干扰。改变发射机的DAC的采样频率，使得没有来自发射机的任何DAC图像将导致与次要接收机的干扰。

2. 发明申请

US20110044380A1 DYNAMICALLY CHANGING A TRANSMITTER SAMPLING FREQUENCY FOR A DIGITAL-TO-ANALOG CONVERTER (DAC) TO REDUCE INTERFERENCE FROM DAC IMAGES 有权
标题翻译：动态更改用于数字模拟转换器（DAC）的发射机采样频率，以减少DAC图像的干扰
公开(公告)号：US20110044380A1
公开(公告)日：2011-02-24
申请号：US12823668
申请日：2010-06-25
申请人： Thomas D. Marra , Soon-Seng Lau , Inyup Kang , Arash Mirbagheri
发明人： Thomas D. Marra , Soon-Seng Lau , Inyup Kang , Arash Mirbagheri
IPC分类号： H04B15/00
CPC分类号： H04B1/525 , H03M1/661 , H04B1/0475
摘要： A method for interference reduction is described. The method is implemented in a wireless device. It is determined that a page is going to be received via a secondary receiver. It is also determined that a digital-to-analog converter (DAC) image from a transmitter will cause interference with the secondary receiver when the page is received. A sampling frequency of the DAC for the transmitter is changed so that there are not any DAC images from the transmitter that will cause interference with the secondary receiver.
摘要翻译：描述了一种减少干扰的方法。该方法在无线设备中实现。确定将通过次级接收器接收页面。还确定，当接收到页面时，来自发射器的数模转换器（DAC）图像将引起与次级接收机的干扰。改变发射机的DAC的采样频率，使得没有来自发射机的任何DAC图像将导致与次要接收机的干扰。

3. 发明授权

US08867673B2 Selective quantization of decision metrics in wireless communication 有权
标题翻译：无线通信决策量度的选择量化
公开(公告)号：US08867673B2
公开(公告)日：2014-10-21
申请号：US13181209
申请日：2011-07-12
申请人： Thomas B. Wilborn , Brian C. Banister , Sungho Yun , Supratik Bhattacharjee , Inyup Kang
发明人： Thomas B. Wilborn , Brian C. Banister , Sungho Yun , Supratik Bhattacharjee , Inyup Kang
IPC分类号： H04L27/06
CPC分类号： H04L25/03184 , H04L25/067
摘要： A method for quantizing decision metrics (e.g., log likelihood ratios (LLRs)) for reduction of memory requirements in wireless communication is described. The method includes selecting a quantization algorithm. The quantization algorithm may be selected as a function of a characteristic of a decision metric representative of a transport block received over a communication channel, a characteristic of the transport block, or a condition of the communication channel. The method further includes quantizing the decision metric using the selected quantization algorithm to generate at least one quantized decision metric representative of the transport block. The method further includes storing the quantized decision metric and an indicia of the selected quantization algorithm to enable recovery of the decision metric representative of the transport block prior to decoding.
摘要翻译：描述了用于量化用于减少无线通信中的存储器要求的决策度量（例如，对数似然比（LLR））的方法。该方法包括选择量化算法。可以根据表示通过通信信道接收的传输块，传输块的特性或通信信道的条件的决策度量的特性来选择量化算法。该方法还包括使用所选择的量化算法对决策度量进行量化，以生成表示传输块的至少一个量化决策度量。该方法还包括存储量化的决策度量和所选量化算法的标记，以使得能够在解码之前恢复表示传输块的决策度量。

4. 发明授权

US08773944B2 Concurrent multiple-dimension word-addressable memory architecture 有权
标题翻译：并行多维字符寻址存储器架构
公开(公告)号：US08773944B2
公开(公告)日：2014-07-08
申请号：US13368752
申请日：2012-02-08
申请人： Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
发明人： Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
IPC分类号： G11C7/10
CPC分类号： G11C8/10 , G06F12/0207 , G11C8/16 , H03M13/2707 , H03M13/2764
摘要： An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
摘要翻译：公开了一种N维可寻址存储器。存储器包括位元组的N维阵列和配置为使用N维度寻址（NDA）来寻址每个位单元的逻辑，其中N至少为2，并且位单元阵列可由N个正交地址空间寻址。 N维可寻址存储器的每个位单元包括位存储元件，N个字线和N个位线。

5. 发明授权

US08706120B2 Mobile telecommunication system with adaptive handoff mechanism and method of operation thereof 有权
标题翻译：具有自适应切换机制的移动电信系统及其操作方法
公开(公告)号：US08706120B2
公开(公告)日：2014-04-22
申请号：US13324988
申请日：2011-12-13
申请人： Insoo Hwang , Jungwon Lee , Heejin Roh , Inyup Kang
发明人： Insoo Hwang , Jungwon Lee , Heejin Roh , Inyup Kang
IPC分类号： H04W4/00 , H04W36/00
CPC分类号： H04W36/245
摘要： A method of operation of a mobile telecommunication system includes: measuring a measured target power and a measured server power; predicting a future target power and a future server power for a prediction tap number from when the measured target power and the measured server power are measured; computing an estimation error and a prediction error associated with the future target power and the future server power; determining a handoff hysteresis level based on the estimation error and the prediction error; and sending a handoff trigger for transferring a mobile station from a server station to a target station when the future target power minus both the future server power and the handoff hysteresis level is greater than zero.
摘要翻译：一种移动通信系统的操作方法包括：测量测量的目标功率和测量的服务器功率; 从测量的目标功率和测量的服务器功率测量起，预测未来目标功率和未来服务器功率的预测抽头数; 计算与未来目标功率和未来服务器功率相关联的估计误差和预测误差; 基于估计误差和预测误差确定越区切换滞后水平; 以及当将来的目标功率减去未来的服务器功率和切换滞后水平都大于零时，发送用于将移动站从服务器站传送到目标站的切换触发。

6. 发明授权

US08634790B2 Direct conversion receiver architecture with digital fine resolution variable gain amplification 有权
标题翻译：直接转换接收机架构，具有数字精细分辨率可变增益放大
公开(公告)号：US08634790B2
公开(公告)日：2014-01-21
申请号：US11131147
申请日：2005-05-16
申请人： Paul E. Peterzell , Christian Holenstein , Inyup Kang , Tao Li , Matthew L. Severson
发明人： Paul E. Peterzell , Christian Holenstein , Inyup Kang , Tao Li , Matthew L. Severson
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

7. 发明申请

US20130065581A1 MOBILE TELECOMMUNICATION SYSTEM WITH NOISE RATIO ESTIMATION MECHANISM AND METHOD OF OPERATION THEREOF 有权
标题翻译：具有噪声比估计机制的手机电信系统及其操作方法
公开(公告)号：US20130065581A1
公开(公告)日：2013-03-14
申请号：US13590567
申请日：2012-08-21
申请人： Insoo Hwang , Heejin Roh , Jungwon Lee , Inyup Kang
发明人： Insoo Hwang , Heejin Roh , Jungwon Lee , Inyup Kang
IPC分类号： H04W24/00
CPC分类号： H04B17/336 , H04B17/26 , H04B17/345
摘要： A method of operation of a mobile telecommunication system includes: measuring a received reference power; removing a guard portion from the received reference power; determining a noise variance estimate from both a noise region of the received reference power and a noise sample in a signal region of the received reference power, or calculating a dispersion power of a noise region of the received reference power and determining the noise variance estimate based on at least a dispersion power; and calculating a signal to noise ratio from the noise variance estimate for adjusting a receiver device.
摘要翻译：移动通信系统的操作方法包括：测量接收的参考功率; 从所接收的参考功率中去除保护部分; 从所接收的参考功率的噪声区域和接收到的参考功率的信号区域中的噪声样本两者中确定噪声方差估计，或者计算所接收的参考功率的噪声区域的色散功率，并基于至少分散功率; 以及根据用于调整接收机设备的噪声方差估计来计算信噪比。

8. 发明申请

US20120209900A1 COMMUNICATION SYSTEM WITH SIGNAL PROCESSING MECHANISM AND METHOD OF OPERATION THEREOF 有权
标题翻译：具有信号处理机制的通信系统及其操作方法
公开(公告)号：US20120209900A1
公开(公告)日：2012-08-16
申请号：US13163661
申请日：2011-06-17
申请人： Vladislav Sorokine , Jungwon Lee , Sungsoo Kim , Inyup Kang
发明人： Vladislav Sorokine , Jungwon Lee , Sungsoo Kim , Inyup Kang
IPC分类号： G06F17/14 , G06F17/10
CPC分类号： H04L25/0216 , H04L25/022 , H04L27/2647 , H04L2025/03414
摘要： A method of operation of a communication system includes: generating a filter impulse response and a filter time-domain data with a shortening filter; generating a filter frequency response based on the filter impulse response with a filter frequency response calculator; generating a filter frequency-domain data based on the filter time-domain data with a first process unit; and generating a raw channel impulse response with a filter frequency removal unit for removing the filter frequency response from the filter frequency-domain data.
摘要翻译：一种通信系统的操作方法包括：利用缩短滤波器产生滤波器脉冲响应和滤波器时域数据; 利用滤波器频率响应计算器产生基于滤波器脉冲响应的滤波器频率响应; 使用第一处理单元基于所述滤波器时域数据生成滤波器频域数据; 以及用滤波器频率去除单元产生原始信道脉冲响应，以从滤波器频域数据中去除滤波器频率响应。

9. 发明申请

US20120134229A1 CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE 有权
标题翻译：同时存在多个字节的可寻址存储器架构
公开(公告)号：US20120134229A1
公开(公告)日：2012-05-31
申请号：US13368752
申请日：2012-02-08
申请人： Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
发明人： Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
IPC分类号： G11C8/06
CPC分类号： G11C8/10 , G06F12/0207 , G11C8/16 , H03M13/2707 , H03M13/2764
摘要： An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit ceils and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
摘要翻译：公开了一种N维可寻址存储器。存储器包括位细胞的N维阵列和被配置为使用N维度寻址（NDA）寻址每个位单元的逻辑，其中N至少为2，并且位单元阵列可由N个正交地址空间寻址。 N维可寻址存储器的每个位单元包括位存储元件，N个字线和N个位线。

10. 发明申请

US20110105070A1 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US20110105070A1
公开(公告)日：2011-05-05
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H03L5/00 , H04B1/16
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

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