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    • 2. 发明授权
    • Apparatus for sorting data words on the basis of the values of
associated parameters
    • 用于根据相关参数的值对数据字进行排序的装置
    • US4570221A
    • 1986-02-11
    • US651634
    • 1984-09-14
    • Theodorus G. J. A. Martens
    • Theodorus G. J. A. Martens
    • G06F7/22G06F7/24G06F17/30H04L1/00G06F7/08
    • H04L1/0054G06F7/24G06F2207/226
    • Apparatus for quickly sorting a succession of data words on the basis of the value of a specific parameter associated with each data word has a memory divided into M blocks of N storage locations each. A counting device includes a counter for each block, the content of each counter addressing the locations within the corresponding block. During a write operation an input data word and associated parameter are applied to an input, and the value of the parameter is used as a block address; prior to this happening the count in the counter associated with the relevant block is incremented by one. Also present is a priority determining device which, during a read operation, addresses, under the control of all counts in the counting device which indicate a number of data words other than zero in the relevant block, the block of highest priority thereamong, the locations in this block again being addressed by the corresponding counter. After the read operation, the count in the counter corresponding to the block read is decremented by one. If desired a predetermined fraction of the data words having, for example, the lowest parameter values can thus be detected.
    • 基于与每个数据字相关联的特定参数的值来快速排序一连串数据字的装置具有分为每个N个存储位置的M个块的存储器。 计数装置包括每个块的计数器,每个计数器的内容寻址相应块内的位置。 在写入操作期间,输入数据字和相关联的参数被应用于输入,并且参数的值被用作块地址; 在这种情况发生之前,与相关块相关联的计数器中的计数增加1。 还存在优先级确定装置,其在读取操作期间,在计数装置中的所有计数的控制下,在相关块中指示除零之外的数据字的数量,其中优先级最高的块,位置 在这个区块里再次被对应的计数器处理。 在读操作之后,与块读取相对应的计数器中的计数减1。 如果需要,可以检测具有例如最低参数值的数据字的预定分数。
    • 3. 发明授权
    • Demodulator arrangement
    • 解调器安排
    • US4835622A
    • 1989-05-30
    • US71006
    • 1987-07-07
    • Theodorus G. J. A. Martens
    • Theodorus G. J. A. Martens
    • G11B20/06H03D3/24H03L7/14H04N5/928
    • H03D3/244
    • A demodulator arrangement including a phase-locked loop PLL (11) having an output (17) coupled to an input (23) of a hold circuit (24) also includes detection means (27) for detecting an instantaneous interference (FIG. 4b) in the signal present at the input (10) of the PLL (11) and for subsequently generating a control signal (FIG. 4e) which is applied to a control input (29) of the hold circuit. The hold circuit is adapted to retain the signal applied to its input (23) during the time interval (T.sub.3) when the control signal is presented to its control input (27). The detection means (27) are adapted to determine a phase-lock error between the signal at the input of the PLL (11) and the signal at the output (20) of a voltage-controlled oscillator VCO (19) associated with the PLL (11) and to generate the control signal if the phase-lock error exceeds a given value, for example, 45.degree.. A better detection of the instantaneous interferences can be realized with such an arrangement in comparison with the use of the amplitude information (if present) of the signal at the input (10) of the PLL (11).