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    • 5. 发明授权
    • Graphene-based non-boolean logic circuits
    • 基于石墨烯的非布尔逻辑电路
    • US09197215B1
    • 2015-11-24
    • US14268765
    • 2014-05-02
    • The Regents of the University of California
    • Alexander A. BalandinAlexander KhitunRoger Lake
    • H01L29/06H03K19/08H01L47/00H01L29/16H01L29/786H03K19/20B82Y99/00
    • H01L29/16B82Y99/00H01L29/1606H01L29/786H01L29/78648H01L29/78684H01L47/00H03K5/19H03K19/08H03K19/20Y10S977/936
    • A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits.
    • 公开了具有负差分电阻(NDR)区域的双栅晶体管。 双栅极晶体管包括背栅极,设置在背栅极上的零带隙石墨烯层,设置在与顶栅极相邻的零带隙石墨烯层的一部分上的顶栅极,以及排列的漏极 在与顶栅相邻并且从源极位移的零带隙石墨烯层的一部分上。 还包括动态偏置控制器,其被配置为同时扫描跨越Dirac点的源极 - 漏极电压和顶栅极电压,以在NDR区域内提供操作。 采用NDR区域内的操作来实现非布尔逻辑功能。 基于石墨烯的非布尔逻辑电路由所公开的双栅极晶体管的多个构成。 也通过基于石墨烯的非布尔逻辑电路公开了在100 GHz和500 GHz之间运行的模式识别电路。
    • 7. 发明申请
    • GRAPHENE-BASED NON-BOOLEAN LOGIC CIRCUITS
    • 基于GRAPHENE的非博客逻辑电路
    • US20150318856A1
    • 2015-11-05
    • US14268765
    • 2014-05-02
    • The Regents of the University of California
    • Alexander A. BalandinAlexander KhitunRoger Lake
    • H03K19/08H03K19/20H01L29/786H01L47/00H01L29/16
    • H01L29/16B82Y99/00H01L29/1606H01L29/786H01L29/78648H01L29/78684H01L47/00H03K5/19H03K19/08H03K19/20Y10S977/936
    • A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits.
    • 公开了具有负差分电阻(NDR)区域的双栅晶体管。 双栅极晶体管包括背栅极,设置在背栅极上的零带隙石墨烯层,设置在与顶栅极相邻的零带隙石墨烯层的一部分上的顶栅极,以及排列的漏极 在与顶栅相邻并且从源极位移的零带隙石墨烯层的一部分上。 还包括动态偏置控制器,其被配置为同时扫描跨越Dirac点的源极 - 漏极电压和顶栅极电压,以在NDR区域内提供操作。 采用NDR区域内的操作来实现非布尔逻辑功能。 基于石墨烯的非布尔逻辑电路由所公开的双栅极晶体管的多个构成。 也通过基于石墨烯的非布尔逻辑电路公开了在100 GHz和500 GHz之间运行的模式识别电路。