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1. 发明授权

US6148393A Apparatus for generating a valid mask 失效
标题翻译：用于产生有效掩模的装置
公开(公告)号：US6148393A
公开(公告)日：2000-11-14
申请号：US041316
申请日：1998-03-12
申请人： Thang M. Tran , Rammohan Narayan , Shane Southard
发明人： Thang M. Tran , Rammohan Narayan , Shane Southard
IPC分类号： G06F7/76 , G06F9/30 , G06F9/308 , G06F9/38 , G06F9/28
CPC分类号： G06F9/382 , G06F7/764 , G06F9/30018 , G06F9/30149 , G06F9/30152 , G06F9/3802 , G06F9/3853 , G06F2207/3872
摘要： A valid mask generator comprising a series of mask generation blocks. Each block generates a predetermined number of valid mask bits given a predetermined number of start pointer bits and end bits, wherein said predetermined number of valid mask bits generated by each block is less than the total number of bits in the valid mask. The series of mask generation blocks may be connected in series, wherein each block outputs a carry-out signal, and wherein each block receives the carry-out signal from the node before it as a carry-in signal. A method for generating a valid mask from a start pointer and a plurality of end bits is also contemplated.
摘要翻译：包括一系列掩码生成块的有效掩码生成器。每个块产生给定预定数量的开始指针位和结束位的预定数量的有效屏蔽位，其中由每个块产生的所述预定数量的有效屏蔽位小于有效掩码中的总位数。一系列掩模生成块可以串联连接，其中每个块输出进位输出信号，并且其中每个块在作为进位输入信号之前从该节点接收进位输出信号。也可以考虑从开始指针和多个结束比特生成有效掩码的方法。

2. 发明授权

US5983321A Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache 失效
标题翻译：缓存保持寄存器，用于接收指令包，并将指令包提供给预解码单元和指令高速缓存
公开(公告)号：US5983321A
公开(公告)日：1999-11-09
申请号：US815567
申请日：1997-03-12
申请人： Thang M. Tran , Karthikeyan Muthusamy , Rammohan Narayan , Andrew McBride
发明人： Thang M. Tran , Karthikeyan Muthusamy , Rammohan Narayan , Andrew McBride
IPC分类号： G06F9/30 , G06F9/38 , G06F12/00 , G06F13/00
CPC分类号： G06F9/382 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register. In order to reduce the number of ports employed upon the instruction bytes storage used to store cache lines of instructions, the cache holding register retains the cache line until an idle cycle occurs in the instruction bytes storage. The same port ordinarily used for fetching instructions is then used to store the cache line into the instruction bytes storage. In one embodiment, the instruction cache prefetches a succeeding cache line to the cache line which misses. A second cache holding register is employed for storing the prefetched cache line.
摘要翻译：提供采用高速缓存保持寄存器的指令高速缓存器。当从主存储器取出指令字节的高速缓存行时，指令字节从主存储器接收时临时存储到高速缓存保持寄存器中。指令字节是从主存储器接收到的预解码的。如果遇到预测的分支指令，则指令高速缓存内的指令获取机制开始从目标指令路径获取指令。可以在接收到包含预测的分支指令的完整高速缓存行之前启动该获取。只要从目标指令路径获取的指令继续命中指令高速缓存，可以将这些指令提取并分派到采用指令高速缓存的微处理器中。由高速缓存保持寄存器接收包含预测的分支指令的指令字节的高速缓存行的剩余部分。为了减少用于存储高速缓存行指令的指令字节存储器所使用的端口数量，高速缓存保持寄存器保持高速缓存行直到在指令字节存储器中发生空闲周期。通常用于提取指令的相同端口用于将高速缓存行存储到指令字节存储器中。在一个实施例中，指令高速缓存将后续的高速缓存行预取到丢失的高速缓存行。采用第二高速缓存保存寄存器来存储预取的高速缓存行。

3. 发明授权

US5852727A Instruction scanning unit for locating instructions via parallel scanning of start and end byte information 失效
标题翻译：指令扫描单元，用于通过并行扫描开始和结束字节信息来定位指令
公开(公告)号：US5852727A
公开(公告)日：1998-12-22
申请号：US813568
申请日：1997-03-10
申请人： Rammohan Narayan , Thang M. Tran
发明人： Rammohan Narayan , Thang M. Tran
IPC分类号： G06F9/30 , G06F9/308 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30018 , G06F9/30152 , G06F9/3816
摘要： An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.
摘要翻译：公开了一种用于超标量微处理器的指令扫描单元。指令扫描单元处理与多个相邻指令字节相关联的开始，结束和功能字节信息（或预解码数据）。开始字节信息和结束字节信息的处理是独立且并行执行的，并且指令扫描单元产生多个扫描值，该扫描值标识多个连续指令字节内的有效指令。另外，指示扫描单元是可扩展的。可以并行操作多个指令扫描单元以处理较大的多个相邻指令字节。此外，指令扫描单元与扫描并行地检测预解码数据中的错误状况以定位指令。此外，与错误检查和扫描并行定位指令，MROM指令位于调度到MROM单元。

4. 发明授权

US5968163A Microcode scan unit for scanning microcode instructions using predecode data 失效
标题翻译：微码扫描单元，用于使用预解码数据扫描微码指令
公开(公告)号：US5968163A
公开(公告)日：1999-10-19
申请号：US814629
申请日：1997-03-10
申请人： Rammohan Narayan , Shane A. Southard , Thang M. Tran
发明人： Rammohan Narayan , Shane A. Southard , Thang M. Tran
IPC分类号： G06F9/28 , G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/382 , G06F9/28 , G06F9/30152 , G06F9/3017 , G06F9/3816 , G06F9/3867
摘要： An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.
摘要翻译：公开了一种用于超标量微处理器的指令扫描单元。指令扫描单元处理与多个相邻指令字节相关联的开始，结束和功能字节信息（或预解码数据）。开始字节信息和结束字节信息的处理是独立并行执行的，并且指令扫描单元产生多个扫描值，该扫描值标识多个连续指令字节内的有效指令。另外，指示扫描单元是可扩展的。可以并行操作多个指令扫描单元以处理较大的多个相邻指令字节。此外，指令扫描单元与扫描并行地检测预解码数据中的错误状况以定位指令。此外，与错误检查和扫描并行定位指令，MROM指令位于调度到MROM单元。

5. 发明授权

US5898851A Method and apparatus for five bit predecoding variable length instructions for scanning of a number of RISC operations 失效
标题翻译：用于扫描多个RISC操作的五位预解码可变长度指令的方法和装置
公开(公告)号：US5898851A
公开(公告)日：1999-04-27
申请号：US873115
申请日：1997-06-11
申请人： Rammohan Narayan , Thang M. Tran
发明人： Rammohan Narayan , Thang M. Tran
IPC分类号： G06F9/30 , G06F9/345 , G06F9/318 , G06F9/40
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816
摘要： A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte include an end bit and two ROP bits. The ROP bits indicate a number of microinstructions required to implement the instruction. The plurality of predecode bits are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to identify microinstructions. The instruction alignment unit dispatches the microinstructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. Because the instruction alignment unit identifies microinstructions, the multiplexing of instructions from the instruction alignment unit to the decoders is simplified. Accordingly, relatively fast multiplexing may be attained, and high performance may be accommodated.
摘要翻译：提供了一种超标量微处理器，其包括预定解码单元，其被配置为在可变字节长度指令存储在指令高速缓存之前预解码。预解码单元被配置为为每个指令字节生成多个预解码位。与每个指令字节相关联的多个预解码位包括结束位和两个ROP位。 ROP位指示实现该指令所需的微指令数。多个预解码比特统称为预解码标签。指令对齐单元然后使用预解码标签来识别微指令。指令对准单元将微指令同时分配到在超标量微处理器内形成固定发行位置的多个解码单元。由于指令对准单元识别微指令，简化了从指令对准单元到解码器的指令的复用。因此，可以实现相对快速的复用，并且可以适应高性能。

6. 发明授权

US5859992A Instruction alignment using a dispatch list and a latch list 失效
标题翻译：指令对齐使用调度列表和锁存列表
公开(公告)号：US5859992A
公开(公告)日：1999-01-12
申请号：US815566
申请日：1997-03-12
申请人： Thang M. Tran , Rammohan Narayan , Jagadish V. Nayak
发明人： Thang M. Tran , Rammohan Narayan , Jagadish V. Nayak
IPC分类号： G06F9/30 , G06F9/38 , G06F9/00
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： An instruction alignment unit includes a byte queue configured to store instruction blocks. Each instruction block includes a fixed number of instruction bytes and identifies up to a maximum number of instructions within the fixed number of instruction bytes. Additionally, the instruction alignment unit is configured to form a pair of instruction lists: a dispatch list and a latch list. The dispatch list includes instruction locators corresponding to instructions within the instruction blocks stored in the byte queue. Additionally, the first three instructions from instructions blocks being received from the instruction cache during a particular clock cycle are appended to the dispatch list. The dispatch list is used to select instructions from the byte queue for dispatch to the decode units. The latch list is used for receiving instruction locators for the remaining instructions from the instruction blocks received from the instruction cache during the particular clock cycle. Furthermore, the latch list receives instruction locators from the dispatch list which correspond to instructions not selected for dispatch to the decode units. The latch list is stored until a succeeding clock cycle, in which the stored program-ordered list is used as a basis for forming the dispatch list during that succeeding clock cycle. The instruction identification information and instruction bytes corresponding to the instruction can be located by selecting the instructions corresponding to the instruction locators at the front of the dispatch list.
摘要翻译：指令对准单元包括被配置为存储指令块的字节队列。每个指令块包括固定数量的指令字节，并且在固定数目的指令字节内识别最多指令数。此外，指令对准单元被配置为形成一对指令列表：调度列表和锁存列表。调度列表包括对应于存储在字节队列中的指令块内的指令的指令定位符。此外，在特定时钟周期期间从指令高速缓存接收到来自指令块的前三个指令被附加到调度列表。调度列表用于从字节队列中选择用于调度到解码单元的指令。锁存列表用于从特定时钟周期内从指令高速缓存接收到的指令块接收剩余指令的指令定位器。此外，锁存列表从调度列表接收与未被选择用于发送到解码单元的指令对应的指令定位器。存储锁存列表直到下一个时钟周期，其中存储的程序排序列表用作在该后续时钟周期期间形成分派列表的基础。可以通过选择与调度列表前面的指令定位符相对应的指令来定位与该指令相对应的指令识别信息和指令字节。

7. 发明授权

US5748978A Byte queue divided into multiple subqueues for optimizing instruction selection logic 失效
标题翻译：字节队列分为多个子队列，用于优化指令选择逻辑
公开(公告)号：US5748978A
公开(公告)日：1998-05-05
申请号：US650940
申请日：1996-05-17
申请人： Rammohan Narayan , Thang M. Tran
发明人： Rammohan Narayan , Thang M. Tran
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78 , G06F15/82
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/382
摘要： An apparatus for aligning variable byte length instructions to a plurality of issue positions is provided. The apparatus includes a byte queue divided into several subqueues. Each subqueue is maintained such that a first instruction in program order within the subqueue is identified by information stored in a first position within the subqueue, a second instruction in program order within the subqueue is identified by information stored in a second position within the subqueue, etc. When instructions from a subqueue are dispatched, remaining instructions within the subqueue are shifted such that the first of the remaining instructions (in program order) occupies the first position, etc. Instructions are shifted from subqueue to subqueue when each of the instructions within a particular subqueue have been dispatched. The information stored in one subqueue is shifted as a unit to another subqueue independent of the internal shifting of subqueue information. The subqueues are additionally configured to handle instructions which overflow from a first subqueue into a second subqueue. Information pertaining to the overflowing instructions is maintained in the last position within the first subqueue. The information is not shifted when other positions within the subqueue are shifted. In this manner, information regarding an overflowing instruction is again located in a limited number of positions.
摘要翻译：提供了一种用于将可变字节长度指令与多个发行位置对准的装置。该装置包括分为几个子队列的字节队列。维持每个子队列，使得在子队列内以程序顺序排列的第一指令通过存储在子队列内的第一位置的信息来识别，子队列内的程序顺序中的第二指令由存储在子队列内的第二位置的信息来识别，当发送来自子队列的指令时，子队列中的剩余指令被移位，使得剩余指令中的第一个（以程序顺序）占据第一位置等。当每个指令在已经调度了一个特定的子队列。存储在一个子队列中的信息作为一个单元移动到另一个子队列，而不依赖于子队列信息的内部移位。子队列另外配置为处理从第一子队列溢出到第二子队列的指令。关于溢出指令的信息被保持在第一子队列内的最后位置。当子队列中的其他位置移动时，信息不会移动。以这种方式，关于溢出指令的信息再次位于有限数量的位置。

8. 发明授权

US6076146A Cache holding register for delayed update of a cache line into an instruction cache 失效
标题翻译：缓存保持寄存器用于将高速缓存行的延迟更新延迟到指令高速缓存
公开(公告)号：US6076146A
公开(公告)日：2000-06-13
申请号：US310356
申请日：1999-05-12
申请人： Thang M. Tran , Karthikeyan Muthusamy , Rammohan Narayan , Andrew McBride
发明人： Thang M. Tran , Karthikeyan Muthusamy , Rammohan Narayan , Andrew McBride
IPC分类号： G06F9/30 , G06F9/38 , G06F12/00 , G06F13/00
CPC分类号： G06F9/382 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register. In order to reduce the number of ports employed upon the instruction bytes storage used to store cache lines of instructions, the cache holding register retains the cache line until an idle cycle occurs in the instruction bytes storage. The same port ordinarily used for fetching instructions is then used to store the cache line into the instruction bytes storage. In one embodiment, the instruction cache prefetches a succeeding cache line to the cache line which misses. A second cache holding register is employed for storing the prefetched cache line.
摘要翻译：提供采用高速缓存保持寄存器的指令高速缓存器。当从主存储器取出指令字节的高速缓存行时，指令字节从主存储器接收时临时存储到高速缓存保持寄存器中。指令字节是从主存储器接收到的预解码的。如果遇到预测的分支指令，则指令高速缓存内的指令获取机制开始从目标指令路径获取指令。可以在接收到包含预测的分支指令的完整高速缓存行之前启动该获取。只要从目标指令路径获取的指令继续命中指令高速缓存，可以将这些指令提取并分派到采用指令高速缓存的微处理器中。由高速缓存保持寄存器接收包含预测的分支指令的指令字节的高速缓存行的剩余部分。为了减少用于存储高速缓存行指令的指令字节存储器所使用的端口数量，高速缓存保持寄存器保持高速缓存行直到在指令字节存储器中发生空闲周期。通常用于提取指令的相同端口用于将高速缓存行存储到指令字节存储器中。在一个实施例中，指令高速缓存将后续的高速缓存行预取到丢失的高速缓存行。采用第二高速缓存保存寄存器来存储预取的高速缓存行。

9. 发明授权

US5940602A Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations 失效
标题翻译：用于预编码可变字节长度指令以扫描多个RISC操作的方法和装置
公开(公告)号：US5940602A
公开(公告)日：1999-08-17
申请号：US873114
申请日：1997-06-11
申请人： Rammohan Narayan , Thang M. Tran
发明人： Rammohan Narayan , Thang M. Tran
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3816
摘要： A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte include an end bit and an ROP bit that indicates a number of microinstructions required to implement the instruction. The plurality of predecode bits are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to identify microinstructions. The instruction alignment unit dispatches the microinstructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. Because the instruction alignment unit identifies microinstructions, the multiplexing of instructions from the instruction alignment unit to the decoders is simplified. Accordingly, relatively fast multiplexing may be attained, and high performance may be accommodated.
摘要翻译：提供了一种超标量微处理器，其包括预定解码单元，其被配置为在可变字节长度指令存储在指令高速缓存之前预解码。预解码单元被配置为为每个指令字节生成多个预解码位。与每个指令字节相关联的多个预解码位包括结束位和指示实现该指令所需的微指令数量的ROP位。多个预解码比特统称为预解码标签。指令对齐单元然后使用预解码标签来识别微指令。指令对准单元将微指令同时分配到在超标量微处理器内形成固定发行位置的多个解码单元。由于指令对准单元识别微指令，简化了从指令对准单元到解码器的指令的复用。因此，可以实现相对快速的复用，并且可以适应高性能。

10. 发明授权

US5850532A Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched 失效
标题翻译：无效的指令扫描单元，用于检测与正在取出的指令相对应的无效预解码数据
公开(公告)号：US5850532A
公开(公告)日：1998-12-15
申请号：US814628
申请日：1997-03-10
申请人： Rammohan Narayan , Shane A. Southard , Thang M. Tran
发明人： Rammohan Narayan , Shane A. Southard , Thang M. Tran
IPC分类号： G06F9/30 , G06F9/38 , G06F9/00
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816
摘要： An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.
摘要翻译：公开了一种用于超标量微处理器的指令扫描单元。指令扫描单元处理与多个相邻指令字节相关联的开始，结束和功能字节信息（或预解码数据）。开始字节信息和结束字节信息的处理是独立且并行执行的，并且指令扫描单元产生多个扫描值，该扫描值标识多个连续指令字节内的有效指令。另外，指示扫描单元是可扩展的。可以并行操作多个指令扫描单元以处理较大的多个相邻指令字节。此外，指令扫描单元与扫描并行地检测预解码数据中的错误状况以定位指令。此外，与错误检查和扫描并行定位指令，MROM指令位于调度到MROM单元。

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