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1. 发明授权

US07603643B2 Method and system for conducting design explorations of an integrated circuit 有权
标题翻译：用于进行集成电路设计探索的方法和系统
公开(公告)号：US07603643B2
公开(公告)日：2009-10-13
申请号：US11700284
申请日：2007-01-30
申请人： Thaddeus Clay McCracken , Jong-Chang Lee , Ping-Chih Wu , Cecile Nghiem , Kit Lam Cheong , Patrick John Eichenseer
发明人： Thaddeus Clay McCracken , Jong-Chang Lee , Ping-Chih Wu , Cecile Nghiem , Kit Lam Cheong , Patrick John Eichenseer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
摘要翻译：公开了用于进行集成电路设计探索的方法和系统。在一个实施例中，该方法包括获得包括虚拟设计块的集成电路的设计描述，创建用于表示虚拟设计块的代表性网表，其中代表性网表包括一个或多个软设计模型，以及每个软设计模型包括用于对集成电路的一部分进行建模的一个或多个模板单元。该方法还包括根据虚拟设计块的区域要求来定义一个或多个软设计模型的物理属性，其中用柔性形状和引脚位置描述一个或多个软设计模型，执行集成电路的设计探索使用一个或多个软设计模型及其对应的模板单元，并且使用设计探索的结果生成集成电路的代表性实现。

2. 发明申请

US20080184184A1 Method and system for conducting design explorations of an integrated circuit 有权
标题翻译：用于进行集成电路设计探索的方法和系统
公开(公告)号：US20080184184A1
公开(公告)日：2008-07-31
申请号：US11700284
申请日：2007-01-30
申请人： Thaddeus Clay McCracken , Jong-Chang Lee , Ping-Chih Wu , Cecile Nghiem , Kit Lam Cheong , Patrick John Eichenseer
发明人： Thaddeus Clay McCracken , Jong-Chang Lee , Ping-Chih Wu , Cecile Nghiem , Kit Lam Cheong , Patrick John Eichenseer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
摘要翻译：公开了用于进行集成电路设计探索的方法和系统。在一个实施例中，该方法包括获得包括虚拟设计块的集成电路的设计描述，创建用于表示虚拟设计块的代表性网表，其中代表性网表包括一个或多个软设计模型，以及每个软设计模型包括用于对集成电路的一部分进行建模的一个或多个模板单元。该方法还包括根据虚拟设计块的区域要求来定义一个或多个软设计模型的物理属性，其中用柔性形状和引脚位置描述一个或多个软设计模型，执行集成电路的设计探索使用一个或多个软设计模型及其对应的模板单元，并且使用设计探索的结果生成集成电路的代表性实现。

3. 发明授权

US08051397B2 Method and system for conducting design explorations of an integrated circuit 有权
标题翻译：用于进行集成电路设计探索的方法和系统
公开(公告)号：US08051397B2
公开(公告)日：2011-11-01
申请号：US12577402
申请日：2009-10-12
申请人： Thaddeus Clay McCracken , Jong-Chang Lee , Ping-Chih Wu , Cecile Nghiem , Kit Lam Cheong , Patrick John Eichenseer
发明人： Thaddeus Clay McCracken , Jong-Chang Lee , Ping-Chih Wu , Cecile Nghiem , Kit Lam Cheong , Patrick John Eichenseer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
摘要翻译：公开了用于进行集成电路设计探索的方法和系统。在一个实施例中，该方法包括获得包括虚拟设计块的集成电路的设计描述，创建用于表示虚拟设计块的代表性网表，其中代表性网表包括一个或多个软设计模型，以及每个软设计模型包括用于对集成电路的一部分进行建模的一个或多个模板单元。该方法还包括根据虚拟设计块的区域要求来定义一个或多个软设计模型的物理属性，其中用柔性形状和引脚位置描述一个或多个软设计模型，执行集成电路的设计探索使用一个或多个软设计模型及其对应的模板单元，并且使用设计探索的结果生成集成电路的代表性实现。

4. 发明授权

US08516433B1 Method and system for mapping memory when selecting an electronic product 有权
标题翻译：选择电子产品时映射内存的方法和系统
公开(公告)号：US08516433B1
公开(公告)日：2013-08-20
申请号：US12824065
申请日：2010-06-25
申请人： Thaddeus Clay McCracken , Miles P McGowan
发明人： Thaddeus Clay McCracken , Miles P McGowan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.
摘要翻译：描述了一种改进的方法来分析和估计具有未提交逻辑阵列的产品，并将这些产品与电子设计相匹配。该方法可以应用于包括未提交逻辑阵列的任何类型的产品，例如门阵列和现场可编程门阵列。描述了在选择具有未提交逻辑阵列的电子产品的上下文中执行存储器映射的方法。

5. 发明授权

US08386981B1 Method and systems for implementing I/O rings and die area estimations 有权
标题翻译：实现I / O环和芯片面积估算的方法和系统
公开(公告)号：US08386981B1
公开(公告)日：2013-02-26
申请号：US12978279
申请日：2010-12-23
申请人： Miles P. McGowan , Thaddeus Clay McCracken
发明人： Miles P. McGowan , Thaddeus Clay McCracken
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.
摘要翻译：公开了用于生成用于电子设计的I / O环布置的改进的方法，系统和计算机程序产品，以及用于基于I / O环布置进行芯片规划和估计。

6. 发明申请

US20100161303A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND USER INTERFACE FOR PERFORMING POWER INFERENCE 审中-公开
标题翻译：方法，系统，计算机程序产品和用于执行功率干扰的用户界面
公开(公告)号：US20100161303A1
公开(公告)日：2010-06-24
申请号：US12342012
申请日：2008-12-22
申请人： Miles P. McGowan , Joseph P. Jarosz , Thaddeus Clay McCracken
发明人： Miles P. McGowan , Joseph P. Jarosz , Thaddeus Clay McCracken
IPC分类号： G06G7/62 , G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： An improved method, system, user interface, and computer program product is described for performing power-related inferences for an electronic design. According to some approaches, the electronic design is configured to include multiple power domains. Design information is used to infer the existence of power-management structures for and between the power domains in the electronic design. A graphical user interface is provided to visualize the inferred power-related structures and to allow the user to interact with and modify the design information related to power management.
摘要翻译：描述了一种改进的方法，系统，用户界面和计算机程序产品，用于执行电子设计的与功率有关的推论。根据一些方法，电子设计被配置为包括多个电源域。设计信息用于推断电子设计中功率域之间和之间的电源管理结构的存在。提供图形用户界面以可视化推断的功率相关结构，并允许用户与电源管理相关的设计信息进行交互和修改。

7. 发明授权

US08683412B1 Method and system for optimizing placement of I/O element nodes of an I/O ring for an electronic design 有权
标题翻译：用于电子设计优化I / O环的I / O元件节点放置的方法和系统
公开(公告)号：US08683412B1
公开(公告)日：2014-03-25
申请号：US12978328
申请日：2010-12-23
申请人： Thaddeus Clay McCracken , Miles P. McGowan
发明人： Thaddeus Clay McCracken , Miles P. McGowan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.
摘要翻译：公开了用于生成和优化用于电子设计的I / O环布置的改进的方法，系统和计算机程序产品。角填料是可以优化I / O环的一种方法。堆叠I / O组件为优化I / O环提供了另一种方法。

8. 发明授权

US08261215B2 Method and system for performing cell modeling and selection 有权
标题翻译：执行细胞建模和选择的方法和系统
公开(公告)号：US08261215B2
公开(公告)日：2012-09-04
申请号：US12342039
申请日：2008-12-22
申请人： Thaddeus Clay McCracken
发明人： Thaddeus Clay McCracken
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , G06F2217/84
摘要： An improved method, system, and computer program product for selecting components for an early stage electronic design is disclosed. A library of cells is modeled and is characterized by parameter combinations, where the cell modeling information is based upon ranking and scoring of the cells in the cell library. Based upon design specification information for an electronic design, the cell modeling data is used to select one or more representative cells for the early stage design based upon the list of ranked cells. The rankings provide an indication of the appropriateness of the selected cells for the early stage design. The pre-modeling of the cells provides high efficiency at run-time when there is a need to quickly select cells for the early stage design.
摘要翻译：公开了一种用于选择早期电子设计的组件的改进的方法，系统和计算机程序产品。对细胞库建模并通过参数组合来表征，其中细胞建模信息基于细胞库中细胞的评分和评分。基于用于电子设计的设计规范信息，小区建模数据用于基于排序小区的列表来选择用于早期设计的一个或多个代表性小区。这些排名提供了所选择的细胞适用于早期设计的指示。当需要快速选择早期阶段设计的单元时，单元的预建模在运行时提供高效率。

9. 发明授权

US08443323B1 Method and system for implementing a structure to implement I/O rings and die area estimations 有权
标题翻译：实现I / O环和模具面积估计的结构的方法和系统
公开(公告)号：US08443323B1
公开(公告)日：2013-05-14
申请号：US12978313
申请日：2010-12-23
申请人： Miles P. McGowan , Thaddeus Clay McCracken
发明人： Miles P. McGowan , Thaddeus Clay McCracken
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed are improved methods, systems, and computer program products for implementing an I/O ring structure to generate an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement. Nodes in the I/O ring structure are used to track objects in the I/O ring.
摘要翻译：公开了用于实现I / O环结构以生成用于电子设计的I / O环布置以及用于基于I / O环布置进行芯片规划和估计的改进的方法，系统和计算机程序产品。 I / O环结构中的节点用于跟踪I / O环中的对象。

10. 发明授权

US08375344B1 Method and system for determining configurations 有权
标题翻译：用于确定配置的方法和系统
公开(公告)号：US08375344B1
公开(公告)日：2013-02-12
申请号：US12824042
申请日：2010-06-25
申请人： Miles P. McGowan , Thaddeus Clay McCracken , Joseph P. Jarosz , Jeffrey Kim Ng
发明人： Miles P. McGowan , Thaddeus Clay McCracken , Joseph P. Jarosz , Jeffrey Kim Ng
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays.
摘要翻译：描述了一种改进的方法来分析和估计具有未提交逻辑阵列的产品，并将这些产品与电子设计相匹配。该方法可以应用于包括未提交逻辑阵列的任何类型的产品，例如门阵列和现场可编程门阵列。

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