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1. 发明授权

US11205575B2 Method for stripping one or more layers from a semiconductor wafer 有权
公开(公告)号：US11205575B2
公开(公告)日：2021-12-21
申请号：US16552321
申请日：2019-08-27
申请人： Texas Instruments Incorporated
发明人： Byron Joseph Palla , Stephen Alan Keller , Brian Edward Hornung , Brian K. Kirkpatrick , Douglas Ticknor Grider
IPC分类号： H01L21/311 , H01L21/302 , H01L21/762 , H01L27/105 , H01L27/11573
摘要： A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

2. 发明授权

US09269663B2 Single pattern high precision capacitor 有权
标题翻译：单模高精度电容器
公开(公告)号：US09269663B2
公开(公告)日：2016-02-23
申请号：US14077497
申请日：2013-11-12
申请人： Texas Instruments Incorporated
发明人： Stephen Alan Keller , Michael LeRoy Huber
IPC分类号： H01L29/94 , H01L23/522 , H01L49/02
CPC分类号： H01L23/5223 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit contains a high precision capacitor having a bottom plate, a dielectric layer over the bottom plate, a capacitor opening in the dielectric layer exposing, and not overlapping, the bottom plate, a capacitor dielectric layer covering sidewalls and a bottom of the capacitor opening, a top plate covering the capacitor dielectric layer in the capacitor opening, and a capacitor planarizing dielectric layer covering the capacitor top plate in the capacitor opening. A top surface of the capacitor planarizing dielectric layer and a top edge of the capacitor top plate are substantially coplanar. The top plate does not extend laterally beyond the capacitor opening. A method of forming the integrated circuit the high precision capacitor is also disclosed.
摘要翻译：集成电路包括具有底板的高精度电容器，底板上的电介质层，电介质层中的电容器开口暴露底板而不重叠，覆盖电容器的侧壁和底部的电容器介电层开口，覆盖电容器开口中的电容器电介质层的顶板以及覆盖电容器开口中的电容器顶板的电容器平坦化介电层。电容器平坦化电介质层的顶表面和电容器顶板的顶部边缘基本上共面。顶板不横向延伸超过电容器开口。还公开了形成高精度电容器的集成电路的方法。

3. 发明申请

US20200343099A1 METHOD FOR STRIPPING ONE OR MORE LAYERS FROM A SEMICONDUCTOR WAFER 审中-公开
公开(公告)号：US20200343099A1
公开(公告)日：2020-10-29
申请号：US16552321
申请日：2019-08-27
申请人： Texas Instruments Incorporated
发明人： Byron Joseph Palla , Stephen Alan Keller , Brian Edward Hornung , Brian K. Kirpatrick , Douglas Ticknor Grider
IPC分类号： H01L21/311
摘要： A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

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