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1. 发明申请

US20190273601A1 DELAY MODULATED CLOCK DIVISION 审中-公开
公开(公告)号：US20190273601A1
公开(公告)日：2019-09-05
申请号：US16417827
申请日：2019-05-21
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jaiganesh BALAKRISHNAN , Shagun DUSAD , Visvesvaraya PENTAKOTA , Srinivas Kumar Reddy NARU , Sarma Sundareswara GUNTURI , Nagalinga Swamy Basayya AREMALLAPUR
IPC分类号： H04L7/00 , H03K5/14
摘要： A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

2. 发明申请

US20200136631A1 GAIN CORRECTION FOR MULTI-BIT SUCCESSIVE-APPROXIMATION REGISTER 审中-公开
公开(公告)号：US20200136631A1
公开(公告)日：2020-04-30
申请号：US16221323
申请日：2018-12-14
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Srinivas Kumar Reddy NARU , Anand Jerry GEORGE , Shagun DUSAD , Visvesvaraya Appala PENTAKOTA
IPC分类号： H03M1/06 , H03M1/46 , H03M1/12
摘要： A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

3. 发明申请

US20190181842A1 MULTIPLIER-BASED PROGRAMMABLE FILTERS 审中-公开
公开(公告)号：US20190181842A1
公开(公告)日：2019-06-13
申请号：US15839265
申请日：2017-12-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Sundarrajan RANGACHARI , Jaiganesh BALAKRISHNAN , Jawaharlal TANGUDU , Srinivas Kumar Reddy NARU
IPC分类号： H03H17/02
摘要： In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

4. 发明申请

US20200382128A1 GAIN CORRECTION FOR MULTI-BIT SUCCESSIVE-APPROXIMATION REGISTER 审中-公开
公开(公告)号：US20200382128A1
公开(公告)日：2020-12-03
申请号：US16997975
申请日：2020-08-20
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Srinivas Kumar Reddy NARU , Anand Jerry GEORGE , Shagun DUSAD , Visvesvaraya Appala PENTAKOTA
IPC分类号： H03M1/06 , H03M1/12 , H03M1/46
摘要： A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

5. 发明申请

US20190280703A1 GAIN AND MEMORY ERROR ESTIMATION IN A PIPELINE ANALOG TO DIGITAL CONVERTER 审中-公开
公开(公告)号：US20190280703A1
公开(公告)日：2019-09-12
申请号：US16249225
申请日：2019-01-16
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy NARU , Narasimhan RAJAGOPAL , Shagun DUSAD , Viswanathan NAGARAJAN , Visvesvaraya Appala PENTAKOTA
IPC分类号： H03M1/06 , H03M1/00 , H03M1/04
摘要： In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

6. 发明申请

US20190007071A1 ERROR CORRECTING ANALOG-TO-DIGITAL CONVERTERS 审中-公开
公开(公告)号：US20190007071A1
公开(公告)日：2019-01-03
申请号：US16125826
申请日：2018-09-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Viswanathan NAGARAJAN , Srinivas Kumar Reddy NARU , Narasimhan RAJAGOPAL
IPC分类号： H03M13/39 , H03M13/11 , H03M1/12 , H03M1/10
CPC分类号： H03M13/39 , H03M1/0641 , H03M1/1014 , H03M1/1245 , H03M1/164 , H03M13/1145
摘要： A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.

7. 发明申请

US20170041013A1 HISTOGRAM BASED ERROR ESTIMATION AND CORRECTION 有权
标题翻译：基于组织学的错误估计和校正
公开(公告)号：US20170041013A1
公开(公告)日：2017-02-09
申请号：US15231415
申请日：2016-08-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Viswanathan NAGARAJAN , Srinivas Kumar Reddy NARU , Ratna Kumar Venkata PARUPUDI
IPC分类号： H03M1/10 , H03M1/20
CPC分类号： H03M1/0641 , H03M1/168
摘要： A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.
摘要翻译：系统包括包括ADC输入端的模数转换器（ADC）; 一个ADC输出端; 以及被配置为将在ADC输入端接收的模拟信号转换成数字信号的模拟部件。该系统还包括耦合到ADC输出端并被配置为生成关于由ADC产生的多个代码的信息的直方图估计电路，并且确定一个区域，该区域对应于由模拟分量引起的误差的发生 ADC。该系统还包括耦合到ADC输入端并被配置为在模拟信号中引入抖动以产生经修改的模拟信号的抖动电路。

8. 发明申请

US20160315629A1 GAIN AND OFFSET CORRECTION IN AN INTERPOLATION ADC 有权
标题翻译：插值ADC中的增益和偏移校正
公开(公告)号：US20160315629A1
公开(公告)日：2016-10-27
申请号：US14871373
申请日：2015-09-30
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy NARU , Nagarajan VISWANATHAN , Visvesvaraya PENTAKOTA
IPC分类号： H03M1/06 , H03M1/12 , H03M1/36 , H03M1/00
CPC分类号： H03M1/0609 , H03M1/203 , H03M1/361
摘要： In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
摘要翻译：在所描述的示例中，模数转换器（ADC）包括主ADC和参考ADC。主ADC响应于输入信号产生区域信息信号和数字输出。参考ADC从主ADC接收多个参考电压。多个参考电压包括第一参考电压和第二参考电压。参考ADC根据输入信号，第一参考电压和第二参考电压产生参考输出。减法器响应于数字输出和参考输出产生一个误差信号。响应于区域信息信号，误差信号和参考输出，逻辑块产生第一偏移校正信号，第二偏移校正信号和增益失配信号中的一个。

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