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1. 发明授权

US10635405B2 Homogenous atomic pattern for double, add, and subtract operations for digital authentication using elliptic curve cryptography 有权
公开(公告)号：US10635405B2
公开(公告)日：2020-04-28
申请号：US16035440
申请日：2018-07-13
申请人： Texas Instruments Incorporated
发明人： Eric Thierry Peeters
IPC分类号： G06F7/72 , H04L9/00 , H04L9/30 , H04L9/32
CPC分类号： G06F7/725 , H04L9/003 , H04L9/3066 , H04L9/3252 , H04L2209/805
摘要： A method of performing finite field addition and doubling operations in an elliptic curve cryptography (ECC) authentication scheme as a countermeasure to side-channel attack. The addition and doubling operations are executed using atomic patterns that involve the same sequence and number of operation types, so that the noise consumption and electromagnetic emanation profile of circuitry performing the operations is identical regardless of operation. A subtraction operation using such an atomic pattern is also disclosed.

2. 发明授权

US10216484B2 Random number generation with ferroelectric random access memory 有权
公开(公告)号：US10216484B2
公开(公告)日：2019-02-26
申请号：US14301307
申请日：2014-06-10
申请人： Texas Instruments Incorporated
发明人： Eric Thierry Peeters , William Francis Kraus , Manuel Gilberto Aguilar , John Anthony Rodriguez
IPC分类号： G06F12/02 , G06F7/58 , G11C7/20 , G11C29/04 , G11C11/22 , G11C29/44
摘要： A system on chip (SoC) may include a nonvolatile ferroelectric random access memory (FRAM). A random number may be created by applying operating power to the ferroelectric random access memory (FRAM) device and reading a sequence of virgin memory locations within the FRAM device to produce the random number sequence. The sequence of virgin memory locations had previously never been written. The random number may be produced during an initial boot of the SoC, for example. Alternatively, the random number may be saved by a test station during testing of the FRAM device after fabrication of the FRAM device. A memory test of the FRAM may then be performed, after which the random number may be stored in a defined location in the FRAM.

3. 发明申请

US20150355886A1 Random Number Generation with Ferroelectric Random Access Memory 审中-公开
标题翻译：随机数生成与铁电随机存取存储器
公开(公告)号：US20150355886A1
公开(公告)日：2015-12-10
申请号：US14301307
申请日：2014-06-10
申请人： Texas Instruments Incorporated
发明人： Eric Thierry Peeters , William Francis Kraus , Manuel Gilberto Aguilar , John Anthony Rodriguez
IPC分类号： G06F7/58 , G11C11/22
CPC分类号： G06F7/588 , G11C7/20 , G11C11/225 , G11C29/04 , G11C2029/4402
摘要： A system on chip (SoC) may include a nonvolatile ferroelectric random access memory (FRAM). A random number may be created by applying operating power to the ferroelectric random access memory (FRAM) device and reading a sequence of virgin memory locations within the FRAM device to produce the random number sequence. The sequence of virgin memory locations had previously never been written. The random number may be produced during an initial boot of the SoC, for example. Alternatively, the random number may be saved by a test station during testing of the FRAM device after fabrication of the FRAM device. A memory test of the FRAM may then be performed, after which the random number may be stored in a defined location in the FRAM.
摘要翻译：片上系统（SoC）可以包括非易失性铁电随机存取存储器（FRAM）。可以通过向铁电随机存取存储器（FRAM）装置施加操作功率并读取FRAM装置内的一系列原始存储器位置来产生随机数序列来产生随机数。以前从未写过处女记忆位置的顺序。例如，可以在SoC的初始引导期间产生随机数。或者，在FRAM设备制造之后，在测试FRAM设备期间，随机数可由测试台保存。然后可以执行FRAM的存储器测试，之后可以将随机数存储在FRAM中的定义的位置。

4. 发明授权

US10536441B2 Thread ownership of keys for hardware-accelerated cryptography 有权
公开(公告)号：US10536441B2
公开(公告)日：2020-01-14
申请号：US15244208
申请日：2016-08-23
申请人： Texas Instruments Incorporated
发明人： Eric Thierry Peeters , Gregory Allen North
IPC分类号： G06F21/74 , H04L29/06
摘要： An embedded processor with a cryptographic co-processor operating in a multithreading environment, with inter-thread security for cryptography operations. A secure memory block accessible by the co-processor stores a plurality of key entries, each key entry storing data corresponding to a cryptography key, and a thread owner field that identifies an execution thread is associated with that key. A central processing unit issues a call to the co-processor to execute a cryptography operation along with a key identifier for the key to be used, and a thread identifier indicating the current execution thread. The co-processor compares the thread identifier received from the CPU with the thread owner field of the key entry corresponding to the key identifier. If the thread identifier matches the thread owner in the key entry, the key is retrieved from the secure memory block for use by the co-processor for the cryptography operation.

5. 发明授权

US09600239B2 Cryptographic accelerator 有权
公开(公告)号：US09600239B2
公开(公告)日：2017-03-21
申请号：US14455261
申请日：2014-08-08
申请人： Texas Instruments Incorporated
发明人： Eric Thierry Peeters , Hamza Fraz
IPC分类号： G06F7/72 , G06F21/72
CPC分类号： G06F7/723 , G06F7/72 , G06F7/728 , G06F21/72
摘要： A cryptographic accelerator performs various modular arithmetic operations producing unreduced results bounded by the double of the modulus (i.e.: 2*M). In doing so, various processing elements of an ALU of the cryptographic accelerator can begin to process respective data word portions of a modular arithmetic operations before the entirety of one or more operands are loaded. Similarly, various processing elements may begin to store their respective data word portions of a modular arithmetic result before the entirety of the result is calculated.

6. 发明授权

US09231770B2 Combined digital certificate 有权
标题翻译：组合数字证书
公开(公告)号：US09231770B2
公开(公告)日：2016-01-05
申请号：US14329237
申请日：2014-07-11
申请人： Texas Instruments Incorporated
发明人： Eric Thierry Peeters
IPC分类号： H04L29/06 , H04L9/32 , H04L9/30
CPC分类号： H04L9/3263 , H04L9/006 , H04L9/3066 , H04L9/3268
摘要： A system can comprise a memory to store computer readable instructions and a processing unit to access the memory and to execute the computer readable instructions. The computer readable instructions can comprise a certificate manager configured to request generation of N number of random values, where N is an integer greater than or equal to one. The certificate manager can also be configured to request a digital certificate from at least one certificate authority of at least two different certificate authorities. The request can include a given one of the N number of random values. The certificate manager can also be configured to generate a private key of a public-private key pair, wherein the private key is generated based on a private key of each of the least two certificate authorities.
摘要翻译：系统可以包括用于存储计算机可读指令的存储器和用于访问存储器并执行计算机可读指令的处理单元。计算机可读指令可以包括被配置为请求生成N个随机值的证书管理器，其中N是大于或等于1的整数。证书管理器还可以被配置为从至少两个不同的证书颁发机构的至少一个证书颁发机构请求数字证书。该请求可以包括N个随机值中的给定的一个。证书管理器还可以被配置为生成公私密钥对的私钥，其中基于至少两个证书颁发机构中的每一个的私钥生成私钥。

7. 发明申请

US20210406020A1 PROCESSOR WITH HARDWARE SUPPORTED MEMORY BUFFER OVERFLOW DETECTION 有权
公开(公告)号：US20210406020A1
公开(公告)日：2021-12-30
申请号：US17469018
申请日：2021-09-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Erik Newton Shreve , Eric Thierry Peeters , Per Torstein Roine
IPC分类号： G06F9/30 , G06F9/32
摘要： A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.

8. 发明授权

US10613864B2 Processor with hardware supported memory buffer overflow detection 有权
公开(公告)号：US10613864B2
公开(公告)日：2020-04-07
申请号：US15923121
申请日：2018-03-16
申请人： Texas Instruments Incorporated
发明人： Erik Newton Shreve , Eric Thierry Peeters , Per Torstein Roine
IPC分类号： G06F9/30 , G06F9/32
CPC分类号： G06F9/30145 , G06F9/321
摘要： A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.

9. 发明申请

US20180063100A1 Thread Ownership of Keys for Hardware-Accelerated Cryptography 审中-公开
公开(公告)号：US20180063100A1
公开(公告)日：2018-03-01
申请号：US15244208
申请日：2016-08-23
申请人： Texas Instruments Incorporated
发明人： Eric Thierry Peeters , Gregory Allen North
IPC分类号： H04L29/06
摘要： An embedded processor with a cryptographic co-processor operating in a multithreading environment, with inter-thread security for cryptography operations. A secure memory block accessible by the co-processor stores a plurality of key entries, each key entry storing data corresponding to a cryptography key, and a thread owner field that identifies an execution thread is associated with that key. A central processing unit issues a call to the co-processor to execute a cryptography operation along with a key identifier for the key to be used, and a thread identifier indicating the current execution thread. The co-processor compares the thread identifier received from the CPU with the thread owner field of the key entry corresponding to the key identifier. If the thread identifier matches the thread owner in the key entry, the key is retrieved from the secure memory block for use by the co-processor for the cryptography operation.

10. 发明申请

US20170242662A1 Homogenous Atomic Pattern for Double, Add, and Subtract Operations for Digital Authentication Using Elliptic Curve Cryptography 审中-公开
公开(公告)号：US20170242662A1
公开(公告)日：2017-08-24
申请号：US15590217
申请日：2017-05-09
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Eric Thierry Peeters
IPC分类号： G06F7/72 , H04L9/30 , H04L9/32 , H04L9/00
CPC分类号： G06F7/725 , H04L9/003 , H04L9/3066 , H04L9/3252 , H04L2209/805
摘要： A method of performing finite field addition and doubling operations in an elliptic curve cryptography (ECC) authentication scheme as a countermeasure to side-channel attack. The addition and doubling operations are executed using atomic patterns that involve the same sequence and number of operation types, so that the noise consumption and electromagnetic emanation profile of circuitry performing the operations is identical regardless of operation. A subtraction operation using such an atomic pattern is also disclosed.

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