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1. 发明授权

US07105387B2 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07105387B2
公开(公告)日：2006-09-12
申请号：US10961236
申请日：2004-10-12
申请人： Tadaharu Minato , Tetsuya Nitta
发明人： Tadaharu Minato , Tetsuya Nitta
IPC分类号： H01L21/332
CPC分类号： H01L29/7824 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0834 , H01L29/66712 , H01L29/7802 , H01L29/7823
摘要： A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.Thereby, the main withstand voltage of a power semiconductor device to which a three dimensional multi-RESURF principle is applied, wherein the element withstand voltage is specifically in the broad range of 20 to 6000 V, can be improved and the trade-off relationship between the main withstand voltage and the ON resistance can also be improved, so that an inexpensive semiconductor device of which the power loss is small and of which the size of the chip is small can be obtained.In addition, a trench of a dotted line trench (DLT) structure and a manufacturing method corresponding to this can be used, so that a semiconductor device with a good yield can be obtained at low cost.
摘要翻译：本发明的半导体器件具有p +重复结构，其中p型杂质区（4）和n型漂移区（3）并排排列的结构重复两次或更多次，并且位于该pn重复结构的最外部的p型杂质区（4）或n型漂移区（3）的低浓度区域具有最低的杂质浓度或者在所有的 p型杂质区（4）和形成pn重复结构的n型漂移区（3）。因此，可以提高应用了三维多RESURF原理的功率半导体器件的主耐受电压，其中元件耐受电压特别是在20-6000V的宽范围内，并且可以改善其间的权衡关系也可以提高主耐受电压和导通电阻，从而可以获得功率损耗小且芯片尺寸小的便宜的半导体装置。此外，可以使用虚线沟槽（DLT）结构的沟槽和对应于此的制造方法，从而可以以低成本获得具有良好产率的半导体器件。

2. 发明授权

US06821824B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06821824B2
公开(公告)日：2004-11-23
申请号：US10257775
申请日：2002-10-17
申请人： Tadaharu Minato , Tetsuya Nitta
发明人： Tadaharu Minato , Tetsuya Nitta
IPC分类号： H01L21332
CPC分类号： H01L29/7824 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0834 , H01L29/66712 , H01L29/7802 , H01L29/7823
摘要： A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure. Thereby, the main withstand voltage of a power semiconductor device to which a three dimensional multi-RESURF principle is applied, wherein the element withstand voltage is specifically in the broad range of 20 to 6000 V, can be improved and the trade-off relationship between the main withstand voltage and the ON resistance can also be improved, so that an inexpensive semiconductor device of which the power loss is small and of which the size of the chip is small can be obtained. In addition, a trench of a dotted line trench (DLT) structure and a manufacturing method corresponding to this can be used, so that a semiconductor device with a good yield can be obtained at low cost.
摘要翻译：本发明的半导体器件具有p +重复结构，其中p型杂质区（4）和n型漂移区（3）并排排列的结构重复两次或更多次，并且位于该pn重复结构的最外部的p型杂质区（4）或n型漂移区（3）的低浓度区域具有最低的杂质浓度或者在所有的 p型杂质区（4）和形成pn重复结构的n型漂移区（3）。因此，应用了三维多RESURF原理的功率半导体器件的主耐压，其中元件耐电压特别是在20〜6000V的宽范围内，可以提高主耐压和导通电阻之间的权衡关系，从而可以降低功率损耗小的便宜的半导体器件并且其芯片的尺寸小。此外，可以使用虚线沟槽（DLT）结构的沟槽和与其对应的制造方法，使得具有良好产率的半导体器件可以是以低成本获得。

3. 发明授权

US06518144B2 Semiconductor device having trenches and process for same 有权
标题翻译：具有沟槽的半导体器件及其工艺
公开(公告)号：US06518144B2
公开(公告)日：2003-02-11
申请号：US09813791
申请日：2001-03-22
申请人： Tetsuya Nitta , Tadaharu Minato
发明人： Tetsuya Nitta , Tadaharu Minato
IPC分类号： H01L2176
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/76237 , H01L21/823487 , H01L27/088 , H01L29/0634 , H01L29/0653 , H01L29/66712 , Y10S148/05
摘要： The elements and the trenches are arranged alternately, in repetition, on the main surface of a semiconductor substrate, each of the plurality of elements arranged alternately, in repetition, with the trenches has a configuration (for example, STM) which operates in the same operational mode, and an insulating layer, which is filled into the trenches, and doesn't have a void at a position (the position shallower than the broken line L) shallower than the pn junction to which the largest electric field in the element is applied. Thereby, a semiconductor device and a process for the same, where voids inside of the trenches can be reduced and the film thickness of the insulating film, for filling in the trenches which remain on the surface of the semiconductor substrate, can be made thinner, can be gained through a simple method.
摘要翻译：元件和沟槽重复地交替布置在半导体衬底的主表面上，与沟槽重复地交替布置的多个元件中的每一个元件具有在相同操作中的构造（例如，STM）操作模式和绝缘层，其被填充到沟槽中，并且在比元件中最大电场的pn结浅的位置（比虚线L浅的位置）处不具有空隙应用。因此，可以减小沟槽内部的空隙的半导体器件及其制造方法，并且可以使用于填充留在半导体衬底表面上的沟槽中的绝缘膜的膜厚更薄，可以通过简单的方法获得。

4. 发明申请

US20050048701A1 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050048701A1
公开(公告)日：2005-03-03
申请号：US10961236
申请日：2004-10-12
申请人： Tadaharu Minato , Tetsuya Nitta
发明人： Tadaharu Minato , Tetsuya Nitta
IPC分类号： H01L21/265 , H01L21/266 , H01L21/336 , H01L29/06 , H01L29/78 , H01L29/22 , H01L21/332 , H01L21/44 , H01L33/00
CPC分类号： H01L29/7824 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0834 , H01L29/66712 , H01L29/7802 , H01L29/7823
摘要： A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure. Thereby, the main withstand voltage of a power semiconductor device to which a three dimensional multi-RESURF principle is applied, wherein the element withstand voltage is specifically in the broad range of 20 to 6000 V, can be improved and the trade-off relationship between the main withstand voltage and the ON resistance can also be improved, so that an inexpensive semiconductor device of which the power loss is small and of which the size of the chip is small can be obtained. In addition, a trench of a dotted line trench (DLT) structure and a manufacturing method corresponding to this can be used, so that a semiconductor device with a good yield can be obtained at low cost.
摘要翻译：本发明的半导体器件具有p +重复结构，其中p型杂质区（4）和n型漂移区（3）并排排列的结构重复两次或更多次，并且位于该pn重复结构的最外部的p型杂质区（4）或n型漂移区（3）的低浓度区域具有最低的杂质浓度或者在所有的 p型杂质区（4）和形成pn重复结构的n型漂移区（3）。因此，可以提高应用了三维多RESURF原理的功率半导体器件的主耐受电压，其中元件耐受电压具体在20至6000V的宽范围内，并且可以改善其间的权衡关系也可以提高主耐受电压和导通电阻，从而可以获得功率损耗小且芯片尺寸小的便宜的半导体装置。此外，可以使用虚线沟槽（DLT）结构的沟槽和对应于此的制造方法，从而可以以低成本获得具有良好产率的半导体器件。

5. 发明授权

US06307246B1 Semiconductor resurf devices formed by oblique trench implantation 有权
标题翻译：通过斜沟槽植入形成的半导体复原器件
公开(公告)号：US06307246B1
公开(公告)日：2001-10-23
申请号：US09508896
申请日：2000-03-20
申请人： Tetsuya Nitta , Tadaharu Minato , Akio Uenisi
发明人： Tetsuya Nitta , Tadaharu Minato , Akio Uenisi
IPC分类号： H01L2358
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0873 , H01L29/42368 , H01L29/66712 , H01L29/7813 , H01L29/7827 , H01L29/861 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate has a first main surface with a plurality of trenches 5a sandwiching a region in which p and n diffusions regions 2 and 3 are formed to provide a p-n junction along the depth of the trenches. P diffusion region 2 has a doping concentration profile provided by a p dopant diffused from a sidewall surface of one trench 5a, and n diffusion region 3 has a doping concentration profile provided by an n dopant diffused from a sidewall surface of the other trench 5a. A heavily doped n+ substrate region 1 is provided at a second main surface side of p and n diffusion regions 2 and 3. A depth Ld of trench 5a from the first main surface is greater than a depth Nd of p and n diffusion regions 2, 3 from the first main surface by at least a diffusion length L of the p dopant in p diffusion region 2 or the n dopant in n diffusion region 3 in manufacturing the semiconductor device. A high withstand voltage and low ON-resistance semiconductor device can thus be obtained.
摘要翻译：半导体衬底具有第一主表面，其具有多个沟槽5a，夹持形成p和n扩散区域2和3的区域，以沿着沟槽的深度提供p-n结。 P扩散区2具有由从一个沟槽5a的侧壁表面扩散的p掺杂剂提供的掺杂浓度分布，并且n扩散区3具有由从另一沟槽5a的侧壁表面扩散的n掺杂物提供的掺杂浓度分布。在p和n扩散区域2和3的第二主表面侧设置重掺杂n +衬底区域1.沟槽5a与第一主表面的深度Ld大于p和n扩散区域2的深度Nd， 3，在制造半导体器件时，从第一主表面至少扩散p扩散区2中的p掺杂物的扩散长度L或n扩散区3中的n掺杂剂。因此可以获得高耐压和低导通电阻的半导体器件。

6. 发明授权

US06949798B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06949798B2
公开(公告)日：2005-09-27
申请号：US10416287
申请日：2002-01-28
申请人： Tetsuya Nitta , Tadaharu Minato
发明人： Tetsuya Nitta , Tadaharu Minato
IPC分类号： H01L21/265 , H01L29/06 , H01L29/78 , H01L29/861 , H01L29/76
CPC分类号： H01L29/7811 , H01L21/26586 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/408 , H01L29/7802 , H01L29/7813 , H01L29/7824 , H01L29/861
摘要： The semiconductor device of the present invention has a repeat structure of repeated unit structures in a semiconductor substrate (1), each unit structure having an n type diffusion region (3) and a p type diffusion region (4) in contact with each other to form a pn junction sandwiched between trenches (1a). An impurity amount in the n type diffusion region (3) and an impurity amount in the p type diffusion region (4) in the unit structure are set unequal (or different). Thus, in the semiconductor device having the trenches (1a), favorable breakdown voltage and avalanche breakdown tolerance can be ensured at the same time.
摘要翻译：本发明的半导体器件具有在半导体衬底（1）中重复的单位结构的重复结构，每个单位结构具有n型扩散区（3）和ap型扩散区（4）彼此接触以形成夹在沟槽（1a）之间的pn结。单元结构中的n型扩散区域（3）中的杂质量和p型扩散区域（4）中的杂质量被设定为不等（或不同）。因此，在具有沟槽（1a）的半导体器件中，可以同时确保有利的击穿电压和雪崩击穿公差。

7. 发明授权

US07418889B2 Index table assembly 有权
公开(公告)号：US07418889B2
公开(公告)日：2008-09-02
申请号：US10913547
申请日：2004-08-09
申请人： Tetsuya Nitta
发明人： Tetsuya Nitta
IPC分类号： B23Q16/10
CPC分类号： B23Q1/28 , B23Q16/102 , Y10T74/14 , Y10T74/1494
摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.

8. 发明申请

US20080148901A1 Index table assembly 有权
标题翻译：索引表组装
公开(公告)号：US20080148901A1
公开(公告)日：2008-06-26
申请号：US12068933
申请日：2008-02-13
申请人： Tetsuya Nitta
发明人： Tetsuya Nitta
IPC分类号： B23Q16/10
CPC分类号： B23Q1/28 , B23Q16/102 , Y10T74/14 , Y10T74/1494
摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.
摘要翻译：分度台组件包括旋转台，沿旋转台的旋转轴线的方向与旋转台分离的框架，用于通过沿旋转轴线移动旋转台来使旋转台与框架接触的夹紧装置设置在所述转台和所述框架之间的第一轴承以及设置在所述第一轴承与所述旋转台和所述框架中的一个之间的推动装置，并且至少在所述旋转台和所述框架中将所述第一轴承压靠在所述旋转台和所述框架中的另一个上时旋转台旋转。

9. 发明授权

US07339236B2 Semiconductor device, driver circuit and manufacturing method of semiconductor device 有权
标题翻译：半导体器件，驱动电路及半导体器件的制造方法
公开(公告)号：US07339236B2
公开(公告)日：2008-03-04
申请号：US11352344
申请日：2006-02-13
申请人： Tetsuya Nitta , Yasunori Yamashita , Shinichiro Yanagi , Fumitoshi Yamamoto
发明人： Tetsuya Nitta , Yasunori Yamashita , Shinichiro Yanagi , Fumitoshi Yamamoto
IPC分类号： H01L27/01 , H01L29/76 , H01L21/336
CPC分类号： H01L29/78606 , H01L21/84 , H01L27/12 , H01L29/0847 , H01L29/1083 , H01L29/66659 , H01L29/7835 , H01L29/78624
摘要： The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n− type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.
摘要翻译：本发明提供一种半导体技术，能够抑制晶体管的阈值电压的增加，并且还提高源极区域和漏极区域之间的耐受电压。在SOI衬底中的n + O型半导体层中形成p沟道型MOS晶体管的源极和漏极区域。此外，在半导体层中形成n型杂质区。杂质区域形成在源极区域的正下方的源极区域的整个底部上，并且也形成在源极区域和漏极区域之间的半导体层的正下方。将杂质区域中的杂质浓度的峰值位置设定在源极区域和源极区域之间的半导体层的正上方的正下方的源极区域的最下端。

10. 发明申请

US20090200610A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090200610A1
公开(公告)日：2009-08-13
申请号：US12401889
申请日：2009-03-11
申请人： Tetsuya Nitta , Takayuki Igarashi
发明人： Tetsuya Nitta , Takayuki Igarashi
IPC分类号： H01L27/12
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/761 , H01L21/76281 , H01L21/76283 , H01L29/0684 , H01L29/0692 , H01L29/0852 , H01L29/1095 , H01L29/42368 , H01L29/7317 , H01L29/7824 , H01L29/7835 , H01L29/7881 , H01L29/8611
摘要： An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N− layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.
摘要翻译：在半导体衬底上形成有一个BOX层的N层。在N层中，形成沟槽隔离区域以包围N层以成为元件形成区域。沟槽隔离区形成为从N层的表面到达BOX层。在沟槽隔离区域和N层之间形成P型扩散区域10a。连续形成P型扩散区域而不间断地与围绕元件形成区域的沟槽隔离区域的内侧壁的整个表面接触。在N层的元件形成区域中，形成规定的半导体元件。因此，形成了可靠地建立电绝缘的半导体器件，而不增加元件形成区域占据的面积。

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