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1. 发明授权

US06993597B2 Terminal apparatus 失效
标题翻译：终端设备
公开(公告)号：US06993597B2
公开(公告)日：2006-01-31
申请号：US10639445
申请日：2003-08-13
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： G06F3/00
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

2. 发明申请

US20080207158A1 TERMINAL APPARATUS 有权
标题翻译：终端设备
公开(公告)号：US20080207158A1
公开(公告)日：2008-08-28
申请号：US12112968
申请日：2008-04-30
申请人： Tetsuya NAKAGAWA , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya NAKAGAWA , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： H04B1/26
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

3. 发明授权

US08090398B2 Terminal apparatus 有权
标题翻译：终端设备
公开(公告)号：US08090398B2
公开(公告)日：2012-01-03
申请号：US12112968
申请日：2008-04-30
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： H04M1/00
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

4. 发明申请

US20060085563A1 Terminal apparatus 审中-公开
公开(公告)号：US20060085563A1
公开(公告)日：2006-04-20
申请号：US11289389
申请日：2005-11-30
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： G06F3/00
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

5. 发明授权

US06643713B2 Apparatus has a microprocessor including DSP and a CPU integrated with each other as a single bus master 有权
标题翻译：装置具有包括DSP和CPU的微处理器，它们作为单总线主机彼此集成
公开(公告)号：US06643713B2
公开(公告)日：2003-11-04
申请号：US10028425
申请日：2001-12-28
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： G06F300
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

6. 发明授权

US06353863B1 Terminal 有权
标题翻译：终奌站
公开(公告)号：US06353863B1
公开(公告)日：2002-03-05
申请号：US09051286
申请日：1998-12-01
申请人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
发明人： Tetsuya Nakagawa , Yuji Hatano , Yasuhiro Sagesaka , Toru Baji , Koki Noguchi
IPC分类号： G06F300
CPC分类号： G06F9/3885 , G06F1/3203 , G06F15/7807
摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.
摘要翻译：低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。此外，DSP和CPU的数据输入和输出需要两个外设单元。因此，DSP和CPU之间会发生无关的通信开销。本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

7. 发明授权

US5884092A System for maintaining fixed-point data alignment within a combination CPU and DSP system 失效
标题翻译：用于在CPU和DSP系统组合中保持定点数据对齐的系统
公开(公告)号：US5884092A
公开(公告)日：1999-03-16
申请号：US725481
申请日：1996-10-04
申请人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F5/01 , G06F7/00 , G06F7/76 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38 , G06F15/78 , G06F17/10 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043
摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.The digital signal processing unit is made a calculation unit that handles fixed-point data, and an instruction calling for execution of a fixed-point data calculation is provided separately from the conventional integer calculation instruction. When, in the data transfer between the digital signal processing unit and memories or external circuits, data shorter in bit length than the calculation precision is transferred, the calculation unit has a function to input and output data to and from the higher-order side of the register in which the data is stored and the fixed point data transfer instruction is provided separately from the conventional integer data transfer instruction.This invention can eliminate additional correction processing necessitated when the integer data processing unit is made to execute the digitalsignal processing.
摘要翻译：在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理器被安装在同一个发明中，防止了数量的增加由计算器处理的不同类型的数据引起的处理步骤，从而提高数字信号处理的效率。数字信号处理单元是处理定点数据的计算单元，并且与常规整数计算指令分开提供调用执行定点数据计算的指令。当在数字信号处理单元和存储器或外部电路之间的数据传送中，位长度比传送计算精度更短的数据时，计算单元具有向数据信号处理单元和存储器或外部电路的高阶侧输入和输出数据的功能，存储数据的寄存器和固定点数据传送指令与传统的整数数据传送指令分开提供。本发明可以消除当整数数据处理单元执行数字信号处理时所需的附加校正处理。

8. 发明授权

US06889240B2 Data processing device having a central processing unit and digital signal processing unit 失效
标题翻译：具有中央处理单元和数字信号处理单元的数据处理装置
公开(公告)号：US06889240B2
公开(公告)日：2005-05-03
申请号：US10694771
申请日：2003-10-29
申请人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F5/01 , G06F7/00 , G06F7/76 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38 , G06F15/78 , G06F17/10 , G06F7/38
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043
摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.
摘要翻译：在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

9. 发明授权

US06668266B2 Data processing device having a central processing unit and digital signal processing unit 失效
标题翻译：具有中央处理单元和数字信号处理单元的数据处理装置
公开(公告)号：US06668266B2
公开(公告)日：2003-12-23
申请号：US09973734
申请日：2001-10-11
申请人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043
摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.
摘要翻译：在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

10. 发明授权

US5124583A DC-powered Josephson integrated circuit 失效
标题翻译：直流电源JOSEPHSON集成电路
公开(公告)号：US5124583A
公开(公告)日：1992-06-23
申请号：US650933
申请日：1991-02-05
申请人： Yuji Hatano , Shinichiro Yano , Hiroyuki Mori , Hirozi Yamada , Mikio Hirano
发明人： Yuji Hatano , Shinichiro Yano , Hiroyuki Mori , Hirozi Yamada , Mikio Hirano
IPC分类号： H01L39/22 , G06F7/38 , H01L27/18 , H03K3/38 , H03K19/195
CPC分类号： H01L27/18 , G06F7/381 , H03K19/1952 , H03K3/38 , Y10S505/861 , Y10S505/865
摘要： A DC powered integrated circuit includes a plurality of magnetic flux coupling type Josephson elements. First and second Josephson elements are connected in series to form a first element series circuit of Josephson elements. Third and fourth Josephson elements are connected in series to form a second element series circuit of Josephson elements. The first and second element series circuits are connected in series to form a huffle circuit, with a load inductance, three resistors and a DC current source.

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