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    • 10. 发明授权
    • Memory macro composed of a plurality of memory cells
    • 由多个存储单元构成的存储宏
    • US07706173B2
    • 2010-04-27
    • US11987536
    • 2007-11-30
    • Motohisa Ikeda
    • Motohisa Ikeda
    • G11C11/00
    • G11C11/413G11C5/147G11C11/412
    • In a memory macro which can more largely reduce a leak current of a memory cell in a hold state, a power voltage between a power potential and a reference potential is supplied across power terminals of each CMOS inverter (across source electrodes of loading P channel FETs and source electrodes of driving N channel FETs) forming the memory cell when a word line is on (high level), a hold enable voltage which is lower than the power voltage and equal to or higher than a lower limit voltage for enabling data to be held (voltage between a potential dropped lower than the power potential and the reference potential) is supplied between the power terminals when the word line is turned off (low level), and the power voltage is constantly supplied to a back gate electrode of one FET within each CMOS inverter.
    • 在能够更大程度上减小保持状态下的存储单元的泄漏电流的存储器宏中,在每个CMOS反相器的电源端子(跨越加载P沟道FET的源电极)之间提供功率电势和参考电位之间的电源电压 和驱动N沟道FET的源电极),当字线为高电平时形成存储单元,保持使能电压低于电源电压并且等于或高于下限电压,以使数据成为 当字线关闭(低电平)时,在电源端子之间提供保持(在下降到低于功率电位的电位和参考电位之间的电压),并且电力电压被恒定地提供给一个FET的背栅电极 在每个CMOS反相器内。