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1. 发明授权

US06903426B2 Semiconductor switching device 有权
标题翻译：半导体开关装置
公开(公告)号：US06903426B2
公开(公告)日：2005-06-07
申请号：US10153857
申请日：2002-05-24
申请人： Tetsuro Asano , Toshikazu Hirai , Mikito Sakakibara
发明人： Tetsuro Asano , Toshikazu Hirai , Mikito Sakakibara
IPC分类号： H01L21/822 , H01L21/8232 , H01L27/04 , H01L27/06 , H01L27/095 , H03K17/00 , H01L29/76
CPC分类号： H01L27/0605
摘要： A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 μm and a signal receiving FET has a gate width of 400 μm. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.
摘要翻译：半导体开关器件包括具有不同器件特性的两个FET，公共输入端子和两个输出端子。信号发送FET的栅极宽度为500μm，信号接收FET的栅极宽度为400μm。连接信号传输FET的栅电极和控制端的电阻被紧密地配置成为FET提供扩展空间。尽管尺寸减小，但由于不对称的器件设计，开关器件可以允许22.5dBm的最大功率通过。开关器件在2.4GHz或更高的频率下工作，不使用分流FET。

2. 发明授权

US06946891B2 Switching circuit device 失效
标题翻译：开关电路装置
公开(公告)号：US06946891B2
公开(公告)日：2005-09-20
申请号：US10781941
申请日：2004-02-20
申请人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
发明人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
IPC分类号： H01L27/04 , H01L21/06 , H01L21/338 , H01L21/66 , H01L21/822 , H01L21/8232 , H01L27/02 , H01L27/06 , H01L29/80 , H01L29/812 , H02H9/00 , H03K5/08 , H03K17/00 , H03K17/16 , H03K17/693
CPC分类号： H01L27/0288 , B82Y30/00 , H01L51/426 , H01L2224/48227 , H01L2224/49171 , H01L2924/12032 , H01L2924/00
摘要： Since improvement measures are not taken in regard to the electrostatic breakdown voltage, electrostatic breakdown voltages, between the common input terminal IN—first control terminal Ctl-1, between the common input terminal IN—second control terminal Ctl-2, between the first control terminal Ctl-1—the first output terminal OUT1, and between the second control terminal Ctl-2—the second output terminal OUT2, where both ends of gate Schottky junctions of FETs are lead out to the exterior, are low. To solve the problem, the embodiment of the invention provides a switch circuit device, wherein protecting elements are connected by disposing two electrode pads, for connection to a single control terminal, on a chip and positioning the electrode pads near the common input terminal pad I and an output terminal pad O1 or O2. The electrostatic energies that are applied between the first output terminal OUT1—the first control terminal Ctl-1, between the common input terminal IN—the first control terminal Ctl-1, between the second output terminal OUT2—the second control terminal Ctl-2, and between the common input terminal IN—the second control terminal Ctl-2 can be respectively attenuated to the same degree and most efficiently.
摘要翻译：由于在公共输入端子IN-first控制端子Ct1-1之间的公共输入端子IN-第二控制端子Ctl-2之间的静电击穿电压，静电击穿电压之间的静电击穿电压不在第一控制端子Ctl-1-第一输出端子OUT 1和第二控制端子Ct1-2-第二输出端子OUT2之间的第二输出端子OUT 2，其中FET的栅极肖特基结的两端都被引出到外部。为了解决这个问题，本发明的实施例提供一种开关电路装置，其中保护元件通过在芯片上设置用于连接到单个控制端子的两个电极焊盘连接，并将电极焊盘定位在公共输入端子焊盘I附近和输出端子焊盘O 1或O 2。施加在第一输出端子OUT 1之间的第一控制端子Ct1-1之间的公共输入端子IN-第一控制端子Ct1-1之间的第二输出端子OUT 2之间的静电能量 - 第二控制端子Ct1 -2，并且在公共输入端子IN-第二控制端子Ct1-2之间可以分别以相同的程度和最有效地衰减。

3. 发明授权

US06627956B2 Semiconductor switching device 有权
公开(公告)号：US06627956B2
公开(公告)日：2003-09-30
申请号：US10163873
申请日：2002-06-07
申请人： Tetsuro Asano , Toshikazu Hirai , Mikito Sakakibara
发明人： Tetsuro Asano , Toshikazu Hirai , Mikito Sakakibara
IPC分类号： H01L2362
CPC分类号： H01L27/0605 , H03K17/04106
摘要： A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.

4. 发明授权

US08742506B2 Protecting element having first and second high concentration impurity regions separated by insulating region 有权
标题翻译：保护元件具有由绝缘区域隔开的第一和第二高浓度杂质区域
公开(公告)号：US08742506B2
公开(公告)日：2014-06-03
申请号：US13475375
申请日：2012-05-18
申请人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
发明人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
IPC分类号： H01L29/861
CPC分类号： H01L27/0255 , H01L24/48 , H01L27/0248 , H01L27/0288 , H01L29/66098 , H01L29/80 , H01L29/812 , H01L29/861 , H01L2924/00014 , H01L2224/45099 , H01L2224/85399 , H01L2224/05599
摘要： With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
摘要翻译：使用微波FET，结合的肖特基结电容或PN结电容小，并且这种结对静电弱。然而，利用微波装置，不能使用连接保护二极管的方法，因为这种方法增加了寄生电容并导致高频特性的劣化。为了解决上述问题，具有第一n +型区域 - 第二n +型区域布置的保护元件并联连接在具有PN结，肖特基结或电容器的受保护元件的两个端子之间。由于可以在彼此相邻的第一和第二n +区之间进行放电，所以可以在不增加寄生电容的情况下衰减到达FET工作区域的静电能量。

5. 发明授权

US07732868B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07732868B2
公开(公告)日：2010-06-08
申请号：US10521941
申请日：2002-11-28
申请人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
发明人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
IPC分类号： H01L29/812
CPC分类号： H01L29/812 , H01L27/0248 , H01L27/0255 , H01L29/808
摘要： A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.
摘要翻译：在FET的两个端子之间并联连接包括第一n +型区域，绝缘区域和第二n +型区域的保护元件。由于能够使第一和第二n +区域的放电得以实现，所以到达FET工作区域的静电能量可以衰减而不增加寄生电容。

6. 发明授权

US06573529B2 Semiconductor switching device 有权
公开(公告)号：US06573529B2
公开(公告)日：2003-06-03
申请号：US10152880
申请日：2002-05-24
申请人： Tetsuro Asano , Toshikazu Hirai , Mikito Sakakibara
发明人： Tetsuro Asano , Toshikazu Hirai , Mikito Sakakibara
IPC分类号： H01L2906
CPC分类号： H01L27/0605
摘要： A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

7. 发明申请

US20060151816A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060151816A1
公开(公告)日：2006-07-13
申请号：US10521941
申请日：2002-11-28
申请人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
发明人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
IPC分类号： H01L29/80
CPC分类号： H01L29/812 , H01L27/0248 , H01L27/0255 , H01L29/808
摘要： A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.
摘要翻译：在FET的两个端子之间并联连接包括第一n +型区域，绝缘区域和第二n +型区域的保护元件。由于能够使第一和第二n +区域的放电得以实现，所以到达FET工作区域的静电能量可以衰减而不增加寄生电容。

8. 发明申请

US20050121730A1 Protective device 审中-公开
标题翻译：保护装置
公开(公告)号：US20050121730A1
公开(公告)日：2005-06-09
申请号：US10505438
申请日：2003-09-08
申请人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
发明人： Tetsuro Asano , Mikito Sakakibara , Toshikazu Hirai
IPC分类号： H01L27/02 , H01L29/80 , H01L29/812 , H01L29/861 , H01L29/76
CPC分类号： H01L27/0255 , H01L24/48 , H01L27/0248 , H01L27/0288 , H01L29/66098 , H01L29/80 , H01L29/812 , H01L29/861 , H01L2924/00014 , H01L2924/13055 , H01L2224/45099 , H01L2224/85399 , H01L2224/05599 , H01L2924/00
摘要： With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
摘要翻译：使用微波FET，结合的肖特基结电容或PN结电容小，并且这种结对静电弱。然而，利用微波装置，不能使用连接保护二极管的方法，因为这种方法增加了寄生电容并导致高频特性的劣化。为了解决上述问题，具有第一n + + / - 型区域 - 绝缘区域 - 第二n + + - / - 域区域布置的保护元件并联在受保护元件的两个端子具有PN结，肖特基结或电容器。由于可以在彼此相邻的第一和第二正交区域之间进行放电，所以可以衰减到达FET操作区域的静电能量，而不增加寄生电容。

9. 发明授权

US06867115B2 Compound semiconductor device 有权
标题翻译：复合半导体器件
公开(公告)号：US06867115B2
公开(公告)日：2005-03-15
申请号：US10211311
申请日：2002-08-05
申请人： Tetsuro Asano , Toshikazu Hirai , Takayoshi Higashino , Koichi Hirata , Mikito Sakakibara
发明人： Tetsuro Asano , Toshikazu Hirai , Takayoshi Higashino , Koichi Hirata , Mikito Sakakibara
IPC分类号： H01L21/8252 , H01L27/06 , H01L21/265
CPC分类号： H01L24/05 , H01L21/8252 , H01L24/06 , H01L24/45 , H01L24/48 , H01L27/0605 , H01L2224/04042 , H01L2224/05073 , H01L2224/05556 , H01L2224/05644 , H01L2224/45144 , H01L2224/48463 , H01L2224/48644 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01031 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10329 , H01L2924/12032 , H01L2924/1306 , H01L2924/14 , H01L2924/1423 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 μm for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 μm or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 μm or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.
摘要翻译：由于栅极宽度需要较大以达到低插入损耗，因此传统的化合物半导体开关器件容易具有大的芯片尺寸，并且连接焊盘和电路布线之间的间隔需要大于20μm以获得适当的他们之间的隔离。总体芯片尺寸减小，首先，通过减少在2.4GHz以上频率工作的开关FET的栅极宽度与省略分路FET一起减少到700μm或更小，然后通过减小连接焊盘之间的间隔并且电路布线为20mum以下。通过在连接焊盘的最外部分和衬底之间引入绝缘膜和杂质区域，可以实现分离的这种减少，以防止耗尽层的延伸。该装置的制造方法不需要用于容纳上述结构的任何额外的处理步骤，并且能够制造具有常规装置的五分之一尺寸的装置。

10. 发明授权

US06580107B2 Compound semiconductor device with depletion layer stop region 有权
标题翻译：具有耗尽层停止区域的复合半导体器件
公开(公告)号：US06580107B2
公开(公告)日：2003-06-17
申请号：US09973197
申请日：2001-10-10
申请人： Tetsuro Asano , Toshikazu Hirai , Takayoshi Higashino , Koichi Hirata , Mikito Sakakibara
发明人： Tetsuro Asano , Toshikazu Hirai , Takayoshi Higashino , Koichi Hirata , Mikito Sakakibara
IPC分类号： H01L2980
CPC分类号： H01L24/05 , H01L21/8252 , H01L24/06 , H01L24/45 , H01L24/48 , H01L27/0605 , H01L2224/04042 , H01L2224/05073 , H01L2224/05556 , H01L2224/05644 , H01L2224/45144 , H01L2224/48463 , H01L2224/48644 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01031 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10329 , H01L2924/12032 , H01L2924/1306 , H01L2924/14 , H01L2924/1423 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.
摘要翻译：由于栅极宽度需要较大以达到低插入损耗，因此传统的化合物半导体开关器件容易具有大的芯片尺寸，并且连接焊盘和电路布线之间的间隔需要大于20μm以获得适当的他们之间的隔离。总体芯片尺寸减小，首先，通过减少在2.4GHz以上频率工作的开关FET的栅极宽度与省略分路FET一起减少到700μm或更小，然后通过减小连接焊盘之间的间隔并且电路布线为20mum以下。通过在连接焊盘的最外部分和衬底之间引入绝缘膜和杂质区域，可以实现分离的这种减少，以防止耗尽层的延伸。该装置的制造方法不需要用于容纳上述结构的任何额外的处理步骤，并且能够制造具有常规装置的五分之一尺寸的装置。

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