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1. 发明授权

US5926487A High performance registers for pulsed logic 失效
标题翻译：用于脉冲逻辑的高性能寄存器
公开(公告)号：US5926487A
公开(公告)日：1999-07-20
申请号：US583297
申请日：1996-01-05
申请人： Terry Ivan Chappell , Michael Kevin Ciraula , Max Eduardo De Ycaza , Sang Hoo Dhong , Rudolf Adriaan Haring , Talal Kamel Jaber , Mark Samson Milshtein , Pho Hoang Nguyen , Edward Seewann
发明人： Terry Ivan Chappell , Michael Kevin Ciraula , Max Eduardo De Ycaza , Sang Hoo Dhong , Rudolf Adriaan Haring , Talal Kamel Jaber , Mark Samson Milshtein , Pho Hoang Nguyen , Edward Seewann
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/31853
摘要： A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode. The automatic power reduction feature can be extended to downstream logic.
摘要翻译：描述了可以用作使用脉冲逻辑方法设计的逻辑芯片中的流水线寄存器的高性能寄存器。寄存器具有最小的建立时间，脉冲捕获和脉冲启动。寄存器电路符合并实施脉冲逻辑的电路级测试方法，该方法具有禁止脉冲复位的能力，强制复位和以伪静态模式操作电路。寄存器还符合级别敏感扫描设计（LSSD）方法。还描述了一种符合脉冲逻辑设计方法的状态保持静态主从寄存器，该寄存器具有自动功率降低特征和简化的模块寄存器位设计，其可以容易地适用于静态多米诺或脉冲逻辑。该寄存器也符合LSSD标准。还描述了允许静态传输门输入寄存器符合静态评估测试模式的手段和方法。自动降功能可扩展到下游逻辑。

2. 发明授权

US5748012A Methodology to test pulsed logic circuits in pseudo-static mode 失效
标题翻译：在伪静态模式下测试脉冲逻辑电路的方法
公开(公告)号：US5748012A
公开(公告)日：1998-05-05
申请号：US583300
申请日：1996-01-05
申请人： Michael Patrick Beakes , Barbara Alane Chappell , Terry Ivan Chappell , Bruce Martin Fleischer , Rudolf Adriaan Haring , Talal Kamel Jaber , Edward Seewann
发明人： Michael Patrick Beakes , Barbara Alane Chappell , Terry Ivan Chappell , Bruce Martin Fleischer , Rudolf Adriaan Haring , Talal Kamel Jaber , Edward Seewann
IPC分类号： G01R31/3185 , H03K19/096 , H03K19/003
CPC分类号： G01R31/3185 , H03K19/0963
摘要： A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.
摘要翻译：公开了脉冲逻辑电路测试方法及其电路。方法和电路允许禁止复位脉冲，强制复位的能力以及在伪静态操作模式下测试电路的能力。

3. 发明授权

US06028983A Apparatus and methods for testing a microprocessor chip using dedicated scan strings 失效
标题翻译：使用专用扫描串测试微处理器芯片的装置和方法
公开(公告)号：US06028983A
公开(公告)日：2000-02-22
申请号：US715728
申请日：1996-09-19
申请人： Talal Kamel Jaber
发明人： Talal Kamel Jaber
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/00 , G01R31/318
CPC分类号： G06F11/2236 , G01R31/318536
摘要： A test apparatus and method for design verification of at least one microprocessor chip includes a compatible Joint Task Action Group (JTAG) terminal for access to a plurality of computer functional units contained in the chip. A test input terminal included in the JTAG terminal receives a scan string, the string being coupled to each computer functional unit through a first multiplexer. The scan input string is separated by the JTAG terminal under program control into a series of dedicated scan strings, each dedicated scan string being supplied to a selected functional unit through the first multiplexer. Each functional unit includes start and stop scan clocks for testing the functional under program control using the dedicated scan train for the functional unit. A test output terminal included in the JTAG terminal is coupled to each functional unit through a second multiplexer. The test results of the dedicated scan string under control of the scan clock are supplied to the output terminal through the second multiplexer. The compatible JTAG terminal includes further elements for controlling the scan clocks to select a targeted functional unit for testing purposes while the scan strings for non-targeted functional units remain in an inactive state.
摘要翻译：用于至少一个微处理器芯片的设计验证的测试装置和方法包括用于访问包含在芯片中的多个计算机功能单元的兼容联合任务动作组（JTAG）终端。包括在JTAG终端中的测试输入终端接收扫描串，该串通过第一多路复用器耦合到每个计算机功能单元。扫描输入串由程序控制下的JTAG端子分离为一系列专用扫描串，每个专用扫描串通过第一多路复用器提供给选定的功能单元。每个功能单元包括启动和停止扫描时钟，用于使用功能单元的专用扫描列测试程序控制下的功能。包括在JTAG端子中的测试输出端子通过第二多路复用器耦合到每个功能单元。在扫描时钟的控制下的专用扫描串的测试结果通过第二多路复用器提供给输出端。兼容的JTAG终端包括用于控制扫描时钟以选择用于测试目的的目标功能单元的另外的元件，而用于非目标功能单元的扫描串保持在非活动状态。

4. 发明授权

US6055658A Apparatus and method for testing high speed components using low speed test apparatus 失效
标题翻译：使用低速试验装置测试高速部件的装置和方法
公开(公告)号：US6055658A
公开(公告)日：2000-04-25
申请号：US537647
申请日：1995-10-02
申请人： Talal Kamel Jaber , Johnny James LeBlanc , Ronald Gene Walther
发明人： Talal Kamel Jaber , Johnny James LeBlanc , Ronald Gene Walther
IPC分类号： G01R31/319 , G01R31/28
CPC分类号： G01R31/31903
摘要： A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier circuit for multiplying the test clock signal to a higher second frequency capable of operating the device under test, and a finite state machine for generating a first internal clock for testing the device under test. In a practical embodiment, the internal clock speed may be running at a frequency many multiples of the test clock. Alternatively, a method of testing a device under test (DUT) at design speed includes running a predetermined group of tests with a test device operating at a lower speed than the design speed; incorporating LSSD or boundary scan test techniques in the device under test, together with a frequency multiplying device; generating a global clock for the device under test from the frequency multiplying circuit and using a finite state machine as a synchronizer and pulse generator to control a capture clock with respect to the global clock.
摘要翻译：一种用于测试高速集成电路的系统，包括具有测试时钟的测试装置，该测试时钟具有用于对所测试的集成电路器件进行电平敏感扫描设计（LSSD）测试的第一最大频率，用于将测试时钟信号到能够操作被测器件的较高的第二频率，以及用于产生用于测试被测器件的第一内部时钟的有限状态机。在实际实施例中，内部时钟速度可以以测试时钟的许多倍的频率运行。或者，以设计速度测试被测设备（DUT）的方法包括以比设计速度更低的速度操作的测试设备运行预定组的测试; 将LSSD或边界扫描测试技术与被测设备一起，并配有一个倍频装置; 从倍频电路产生被测器件的全局时钟，并使用有限状态机作为同步器和脉冲发生器来控制相对于全局时钟的捕获时钟。

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