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1. 发明授权

US09444413B2 High bandwidth amplifier 有权
标题翻译：高带宽放大器
公开(公告)号：US09444413B2
公开(公告)日：2016-09-13
申请号：US14432759
申请日：2015-02-04
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Sven Mattisson
IPC分类号： H03F3/68 , H03F1/42 , H03F3/19 , H03F3/60
CPC分类号： H03F1/42 , H03F1/08 , H03F1/223 , H03F3/19 , H03F3/193 , H03F3/605 , H03F3/68 , H03F2200/36 , H03F2200/451
摘要： An amplifier (100) comprising: first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal; a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10); a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10); a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3); a first terminal (T41) of the fourth transistor (M4) coupled to the first output (22), a second terminal (T42) of the fourth transistor (M4) coupled to a fourth voltage rail (24), and a gate (G4) of the fourth transistor (M4) coupled to the second terminal (T32) of the third transistor (M3); and a first capacitive element (C1) coupled between the second terminal (T32) of the third transistor (M3) and the first output (22).

2. 发明授权

US09407478B1 Low power and area bootstrapped passive mixer with shared capacitances 有权
标题翻译：低功率和区域自举无源混频器具有共享电容
公开(公告)号：US09407478B1
公开(公告)日：2016-08-02
申请号：US14838044
申请日：2015-08-27
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Sven Mattisson
IPC分类号： H03D7/14 , H04L25/08 , H04B1/10
CPC分类号： H04L25/08 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165
摘要： In a passive mixer, switches and a capacitance are shared between bootstrapped mixing transistors, reducing the number of components required as compared to prior art bootstrap designs. Shared bootstrap circuits operate in an interleaved fashion between I and Q mixer circuits, at twice the LO frequency. That is, the shared bootstrap circuits in each I mixer circuit charge their capacitors in a first half-period of a clock, and connect the shared capacitor to the gate of an enabled mixing transistor in the second half-period. The shared bootstrap circuits in the Q mixer circuit charge their capacitors in the second half-period, and connect the shared capacitor to the gate of an enabled mixing transistor in the first half-period. One of two mixing transistors connected to each shared bootstrap circuit is alternately enabled during the clock signal half-periods that the shared bootstrap circuit is not charging its capacitor.
摘要翻译：在无源混频器中，开关和电容在自举混频晶体管之间共享，与现有技术的引导设计相比，减少了所需的部件数量。共享引导电路在I和Q混频器电路之间以交错方式工作，为LO频率的两倍。也就是说，每个I混频器电路中的共享自举电路在其第一个半周期内对其电容器充电，并在第二个半周期内将共享电容连接到启用的混合晶体管的栅极。 Q混频器电路中的共享引导电路在后半段对其电容充电，并在上半个周期内将共享电容连接到启用的混合晶体管的栅极。在共享自举电路未对其电容器充电的时钟信号半周期期间，连接到每个共享自举电路的两个混合晶体管中的一个交替使能。

3. 发明授权

US09312818B2 Low-noise amplifier 有权
标题翻译：低噪声放大器
公开(公告)号：US09312818B2
公开(公告)日：2016-04-12
申请号：US14375127
申请日：2013-01-25
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Sven Mattisson , Stefan Andersson
IPC分类号： H03F1/34 , H03F1/30 , H03F1/26 , H03F3/195 , H03F1/56 , H03F3/185
CPC分类号： H03F1/301 , H03F1/26 , H03F1/342 , H03F1/565 , H03F3/185 , H03F3/195 , H03F2200/129 , H03F2200/294 , H03F2200/384 , H03F2200/75
摘要： A common source or common emitter LNA circuit for amplifying signals at an operating frequency f in a receiver circuit is disclosed. The LNA circuit comprises an input transistor arranged to, in operation, be biased to have a transconductance gm at the operating frequency f, and having a first terminal, which is a gate or base terminal, operatively connected to an input terminal of the LNA circuit. The LNA circuit further comprises a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor. Furthermore, the LNA circuit comprises an output capacitor operatively connected between the second terminal of the input transistor and an output terminal of the LNA circuit. The output capacitor has a capacitance value CL
摘要翻译：公开了一种用于在接收机电路中以工作频率f放大信号的公共源极或公共发射极LNA电路。 LNA电路包括输入晶体管，其被设置为在操作中被偏置为具有工作频率f处的跨导gm，并且具有可操作地连接到LNA电路的输入端的第一端子，其是栅极或基极端子。 LNA电路还包括可操作地连接在输入晶体管的第一端子和作为输入晶体管的漏极或集电极端子的第二端子之间的并联反馈电容器。此外，LNA电路包括可操作地连接在输入晶体管的第二端子和LNA电路的输出端子之间的输出电容器。输出电容器具有电容值CL

4. 发明授权

US09106501B2 Quadrature power amplifier having increased efficiency 有权
标题翻译：具有提高效率的正交功率放大器
公开(公告)号：US09106501B2
公开(公告)日：2015-08-11
申请号：US13856206
申请日：2013-04-03
申请人： Telefonaktiebolaget L M Ericsson (Publ)
发明人： Fenghao Mu , Sven Mattisson , Thomas Olsson
IPC分类号： H04L27/20 , H04L27/36 , H03F1/02 , H03F3/24 , H04B1/04 , H03C3/40 , H03C1/00 , H03C1/06
CPC分类号： H04L27/362 , H03C1/00 , H03C1/06 , H03C3/40 , H03C2200/0058 , H03F1/0222 , H03F1/0227 , H03F3/24 , H03F2200/336 , H03F2200/451 , H04B1/0475 , H04B2001/0416 , H04L27/361 , H04L27/368
摘要： A method and system for achieving increased efficiency in a quadrature modulated power amplifier (11) are disclosed. In some embodiments, a supply path (36, 40) and a gain path (38, 42) are provided in each of an I-channel and a Q-channel. The supply path (36, 40) produces a variable voltage and the gain path (38, 42) produces a gain control signal. The variable voltage and gain control signal are used by a variable gain power amplifier (44, 46) to modulate a local oscillator signal to produce a modulated radio signal.
摘要翻译：公开了一种在正交调制功率放大器（11）中实现提高效率的方法和系统。在一些实施例中，在I信道和Q信道中的每一个中提供供应路径（36,40）和增益路径（38,42）。供给路径（36,40）产生可变电压，并且增益路径（38,42）产生增益控制信号。可变电压和增益控制信号由可变增益功率放大器（44,46）用于调制本地振荡器信号以产生调制的无线电信号。

5. 发明授权

US09813187B2 Timing for radio reconfiguration in a mobile communications network 有权
公开(公告)号：US09813187B2
公开(公告)日：2017-11-07
申请号：US14758823
申请日：2014-01-09
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Fredrik Tillman , Bengt Lindoff , Sven Mattisson , Johan Nilsson , Lars Sundström
IPC分类号： H04W4/00 , H04L1/00 , H04W72/04 , H04W52/02
CPC分类号： H04L1/0001 , H04L1/0027 , H04W52/0245 , H04W72/042 , Y02D70/1222 , Y02D70/1242 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/162 , Y02D70/21
摘要： A mobile communications terminal comprising a radio frequency interface configured to operate at least at a first configuration, and a controller, wherein said controller is configured to determine that a reconfiguration of the radio frequency interface is to be performed, determine a timing of the reconfiguration and reconfigure said radio frequency interface to operate at a second configuration at the determined timing, wherein said controller is configured to determine said timing based on the type of reconfiguration to be made.

6. 发明授权

US09806677B2 Amplifier adapted for noise suppression 有权
公开(公告)号：US09806677B2
公开(公告)日：2017-10-31
申请号：US14913466
申请日：2015-03-16
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Sven Mattisson
IPC分类号： H03F3/45 , H03F1/26 , H03F1/32 , H03F3/193 , H03F1/02 , H03F1/48 , H03F3/60 , H04B1/12
CPC分类号： H03F1/26 , H03F1/0205 , H03F1/3211 , H03F1/483 , H03F3/193 , H03F3/45179 , H03F3/607 , H03F2200/06 , H03F2200/294 , H03F2200/333 , H03F2200/451 , H03F2203/45306 , H03F2203/45318 , H04B1/12
摘要： An amplifier (100) adapted for noise suppression comprises a first input (102) for receiving a first input signal and a second input (104) for receiving a second input signal, the first and second input signals constituting a differential pair. A first output (106) delivers a first output signal and a second output (108) delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (MCG1) has a first drain (110) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the first drain (110) flows through the first output (106), and the first transistor (MCG1) further having a first source (112) coupled to the first input (102). A second transistor (MCS1) has a second gate (116) coupled to the first input (102), a second drain (118) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the second drain (118) flows through the second output (108), and the second transistor (MCS1) further having a second source (120) coupled to a first voltage rail (122). A third transistor (MCS2) has a third gate (124) coupled to the second input (104), a third drain (126) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the third drain (126) flows through the first output (106), and the third transistor (MCS2) further having a third source (128) coupled to the first voltage rail (122). A fourth transistor (MCG2) has a fourth drain (130) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the fourth drain (130) flows through the second output (108), and the fourth transistor (MCG2) further having a fourth source (132) coupled to the second input (104). A first load (ZL1) is coupled between the first output (106) and a second voltage rail (136). A second load (ZL2) is coupled between the second output (108) and the second voltage rail (136). A first inductive element (L1) is coupled between the first input (102) and a third voltage rail (138), and a second inductive element (L2) is coupled between the second input (104) and the third voltage rail (138). Transconductance of the first transistor (MCG1) is substantially equal to transconductance of the fourth transistor (MCG2), within ±5%, and transconductance of the second transistor (MCS1) is substantially equal to transconductance of the third transistor (MCS2), within ±5%.

7. 发明授权

US09543978B2 Frequency selective circuit configured to convert an analog input signal to a digital output signal 有权
标题翻译：频率选择电路被配置为将模拟输入信号转换成数字输出信号
公开(公告)号：US09543978B2
公开(公告)日：2017-01-10
申请号：US14769164
申请日：2013-02-21
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Sven Mattisson , Martin Anderson , Pietro Andreani , Mattias Palm
IPC分类号： H03M3/00
CPC分类号： H03M3/464 , H03M3/344 , H03M3/368 , H03M3/454
摘要： A frequency selective circuit configured to convert an analog input signal to a digital output signal comprises an analog-to-digital converter (44) to generate the digital output signal of the circuit based on an analog input signal to the analog-to-digital converter (44); a digital-to-analog converter (46, 47) to generate an analog feedback signal based on the digital output signal from the analog-to-digital converter (44), and an analog filter arranged to generate the analog input signal to the analog-to-digital converter based on the analog feedback signal and an analog input signal to the circuit. The analog filter comprises at least two integrators (41, 42) in series, each having a feedback path comprising the analog-to-digital converter (44) in cascade with a digital-to-analog converter (46, 47), so that the overall noise transfer function of the circuit has at least two zeros in addition to zeros in the noise transfer function of the analog-to-digital converter.
摘要翻译：被配置为将模拟输入信号转换为数字输出信号的频率选择电路包括模数转换器（44），用于根据模数转换器的模拟输入信号产生电路的数字输出信号（44）; 数模转换器（46,47），用于基于来自模数转换器（44）的数字输出信号产生模拟反馈信号;以及模拟滤波器，被配置为产生模拟输入信号基于模拟反馈信号的数模转换器和到电路的模拟输入信号。模拟滤波器包括串联的至少两个积分器（41,42），每个具有包括与数模转换器（46,47）级联的模数转换器（44）的反馈路径，使得除了在模数转换器的噪声传递函数中的零之外，电路的总噪声传递函数具有至少两个零。

8. 发明授权

US09413301B2 Noise canceling low-noise amplifier 有权
标题翻译：降噪低噪声放大器
公开(公告)号：US09413301B2
公开(公告)日：2016-08-09
申请号：US14375131
申请日：2013-01-25
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Sven Mattisson , Stefan Andersson
IPC分类号： H03F1/26 , H03F3/193 , H03F1/56 , H03F3/21
CPC分类号： H03F1/26 , H03F1/56 , H03F3/189 , H03F3/193 , H03F3/195 , H03F3/21 , H03F3/211 , H03F2200/255 , H03F2200/267 , H03F2200/294 , H03F2200/372 , H03F2200/451
摘要： A noise-canceling LNA circuit for amplifying signals at an operating frequency f in a receiver circuit is disclosed. The LNA circuit comprises a first and a second amplifier branch, each having an input terminal connected to an input terminal of the LNA circuit. The first amplifier branch comprises an output terminal for supplying an output current of the first amplifier branch and a common source or common emitter main amplifier. The main amplifier has an input transistor having a first terminal, which is a gate or base terminal, operatively connected to the input terminal of the first amplifier branch, a shunt-feedback capacitor operatively connected between the first terminal of the input transistor and a second terminal, which is a drain or collector terminal, of the input transistor, and an output capacitor operatively connected between the second terminal of the input transistor and the output terminal of the first amplifier branch. The second amplifier branch comprises an output terminal for supplying an output current of the second amplifier branch. The LNA circuit comprises circuitry for combining the output current of the first amplifier branch and the output current of the second amplifier branch, thereby generating a total output current of the LNA circuit.
摘要翻译：公开了一种用于在接收机电路中以工作频率f放大信号的噪声消除LNA电路。 LNA电路包括第一和第二放大器分支，每个分支具有连接到LNA电路的输入端的输入端。第一放大器分支包括用于提供第一放大器支路的输出电流的输出端和公共源或公共发射极主放大器。主放大器具有输入晶体管，其具有可操作地连接到第一放大器分支的输入端的第一端子，其是栅极或基极端子，可操作地连接在输入晶体管的第一端子与第二端子之间的分流反馈电容器端子，其是输入晶体管的漏极或集电极端子，以及可操作地连接在输入晶体管的第二端子和第一放大器支路的输出端子之间的输出电容器。第二放大器分支包括用于提供第二放大器分支的输出电流的输出端子。 LNA电路包括用于组合第一放大器支路的输出电流和第二放大器支路的输出电流的电路，从而产生LNA电路的总输出电流。

9. 发明申请

US20160226454A1 High Bandwidth Amplifier 有权
标题翻译：高带宽放大器
公开(公告)号：US20160226454A1
公开(公告)日：2016-08-04
申请号：US14432759
申请日：2015-02-04
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Sven Mattisson
IPC分类号： H03F1/42 , H03F3/19
CPC分类号： H03F1/42 , H03F1/08 , H03F1/223 , H03F3/19 , H03F3/193 , H03F3/605 , H03F3/68 , H03F2200/36 , H03F2200/451
摘要： An amplifier (100) comprising: first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal; a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10); a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10); a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3); a first terminal (T41) of the fourth transistor (M4) coupled to the first output (22), a second terminal (T42) of the fourth transistor (M4) coupled to a fourth voltage rail (24), and a gate (G4) of the fourth transistor (M4) coupled to the second terminal (T32) of the third transistor (M3); and a first capacitive element (C1) coupled between the second terminal (T32) of the third transistor (M3) and the first output (22).
摘要翻译：一种放大器，包括：第一，第二，第三和第四晶体管（M1，M2，M3，M4），用于输入信号的输入端（10）和用于第一放大信号的第一输出端（22）耦合到第一电压轨（12）的第一晶体管（M1）的第一端（T11），耦合到第三晶体管（M3）的第一端（T31）的第一晶体管（M1）的第二端（T12））和耦合到输入（10）的第一晶体管（M1）的栅极（G1）; 耦合到第二电压轨（14）的第二晶体管（M2）的第一端子（T21），耦合到第一输出端（22）的第二晶体管（M2）的第二端子（T22）和栅极）耦合到所述输入（10）的所述第二晶体管（M2）; 耦合在第三晶体管（M3）的第二端子（T32）和第三电压轨道（20）之间的负载（40）和耦合到偏置节点（16）的第三晶体管（M3）的栅极（G3）用于向第三晶体管（M3）的栅极（G3）施加偏置电压; 耦合到第一输出端（22）的第四晶体管（M4）的第一端子（T41），耦合到第四电压轨道（24）的第四晶体管（M4）的第二端子（T42）和栅极）连接到第三晶体管（M3）的第二端子（T32）的第四晶体管（M4）; 以及耦合在第三晶体管（M3）的第二端子（T32）和第一输出端（22）之间的第一电容元件（C1）。

10. 发明申请

US20160036460A1 A Frequency Selective Circuit Configured to Convert an Analog Input Signal to a Digital Output Signal 有权
标题翻译：配置为将模拟输入信号转换为数字输出信号的频率选择电路
公开(公告)号：US20160036460A1
公开(公告)日：2016-02-04
申请号：US14769164
申请日：2013-02-21
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
发明人： Sven Mattisson , Martin Anderson , Pietro Andreani , Mattias Palm
IPC分类号： H03M3/00
CPC分类号： H03M3/464 , H03M3/344 , H03M3/368 , H03M3/454
摘要： A frequency selective circuit configured to convert an analog input signal to a digital output signal comprises an analog-to-digital converter (44) to generate the digital output signal of the circuit based on an analog input signal to the analog-to-digital converter (44); a digital-to-analog converter (46, 47) to generate an analog feedback signal based on the digital output signal from the analog-to-digital converter (44), and an analog filter arranged to generate the analog input signal to the analog-to-digital converter based on the analog feedback signal and an analog input signal to the circuit. The analog filter comprises at least two integrators (41, 42) in series, each having a feedback path comprising the analog-to-digital converter (44) in cascade with a digital-to-analog converter (46, 47), so that the overall noise transfer function of the circuit has at least two zeros in addition to zeros in the noise transfer function of the analog-to-digital converter.
摘要翻译：被配置为将模拟输入信号转换为数字输出信号的频率选择电路包括模数转换器（44），用于根据模数转换器的模拟输入信号产生电路的数字输出信号（44）; 数模转换器（46,47），用于基于来自模数转换器（44）的数字输出信号产生模拟反馈信号;以及模拟滤波器，被配置为产生模拟输入信号基于模拟反馈信号的数模转换器和到电路的模拟输入信号。模拟滤波器包括串联的至少两个积分器（41,42），每个具有包括与数模转换器（46,47）级联的模数转换器（44）的反馈路径，使得除了在模数转换器的噪声传递函数中的零之外，电路的总噪声传递函数具有至少两个零。

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