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1. 发明授权

US07584237B1 Fast hardware divider 有权
标题翻译：快速硬件分频器
公开(公告)号：US07584237B1
公开(公告)日：2009-09-01
申请号：US11247628
申请日：2005-10-11
申请人： Teik-Chung Tan , Michael Tuuk , Wing-Shek Wong
发明人： Teik-Chung Tan , Michael Tuuk , Wing-Shek Wong
IPC分类号： G06F7/52
CPC分类号： G06F7/49936 , G06F7/49926 , G06F7/535 , G06F7/74
摘要： A method and mechanism for performing division. A processor includes a divider configured to perform arithmetic division operations. Prior to dividing a dividend by a divisor, the divider manipulates the dividend and divisor to reduce the number of bits considered and the computations required to perform the division. The divisor is normalized by eliminating sign bits. The dividend is prescaled to eliminate one or more sign bits. Prescaling of the dividend may not be precise as sign bits of the dividend may be shifted out as groups of bits, rather than individual bits. Prescaling of the dividend may be adjusted to account for the fact that the divider considers multiple bits of the dividend at a time. Subsequent to prescaling and adjustment, the dividend may be adjusted in dependence upon the normalization of the divisor. Further adjustment may be utilized to maintain a significance relationship between the divisor and dividend. Subsequent to further adjustment, the division operation may be completed.
摘要翻译：一种执行划分的方法和机制。处理器包括被配置为执行算术除法运算的分频器。在除数除数除数之前，除法器可以操纵除数和除数，以减少所考虑的比特数和进行除法所需的计算。除数通过消除符号位进行归一化。预先分配股息以消除一个或多个符号位。股息的预分配可能不是精确的，因为除数的符号位可以作为位组而不是单独位移出。可以调整股息的预分配以考虑分配器一次考虑股息的多个位的事实。在预分摊和调整之后，股息可以根据除数的归一化进行调整。可以采用进一步调整来维持除数与股息之间的重要关系。在进一步调整之后，分割操作可以完成。

2. 发明授权

US07783692B1 Fast flag generation 有权
标题翻译：快旗生成
公开(公告)号：US07783692B1
公开(公告)日：2010-08-24
申请号：US11175083
申请日：2005-07-05
申请人： Wing-Shek Wong , Michael E. Tuuk , Teik-Chung Tan
发明人： Wing-Shek Wong , Michael E. Tuuk , Teik-Chung Tan
IPC分类号： G06F7/00
CPC分类号： G06F5/01
摘要： A method and circuit for fast flag generation. The circuit is coupled to receive data to be shifted, the data including a first plurality of bits. A shift count value (including a second plurality of bits) is also received by the circuit, as well as an indication of a direction the data is to be shifted. Based on the shift count value and the indication of direction, the position of a bit within the data is determined. The bit is then output as a flag bit.
摘要翻译：一种用于快旗生成的方法和电路。电路被耦合以接收要移位的数据，该数据包括第一多个位。电路还接收到移位计数值（包括第二多个位），以及数据的移位方向的指示。根据移位计数值和方向指示，确定数据内的位的位置。该位然后作为标志位输出。

3. 发明申请

US20070011432A1 Address generation unit with operand recycling 审中-公开
标题翻译：地址生成单元，操作数回收
公开(公告)号：US20070011432A1
公开(公告)日：2007-01-11
申请号：US11175725
申请日：2005-07-06
申请人： Michael Tuuk , David Kroesche , Wing-Shek Wong
发明人： Michael Tuuk , David Kroesche , Wing-Shek Wong
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/345 , G06F9/3875
摘要： An address generation unit (AGU) including a single adder and a recycling path. The recycling AGU may receive a plurality of operands at a first and at a second selection device to perform a first address generation operation. The adder may sum a portion of the operands to generate an output sum. Then, the output sum may be recycled back to the first selection device via the recycle path. The sum that is output from the adder may be recycled back to the first selection device one or more times via the recycle path depending on whether the first address generation operation requires one or more additional operands to be added to generate a corresponding address. Since the recycling AGU includes only a single adder, it may reduce the hardware necessary to perform the multiple computations that are typically required in an address generation operation without adversely affecting performance.
摘要翻译：包括单个加法器和再循环路径的地址生成单元（AGU）。回收AGU可以在第一和第二选择装置处接收多个操作数，以执行第一地址产生操作。加法器可以对操作数的一部分求和以产生输出和。然后，输出总和可以经由再循环路径再循环回第一选择装置。根据第一地址产生操作是否需要一个或多个附加的操作数来生成相应的地址，从加法器输出的和可以经由再循环路径再次回到第一选择装置一次或多次。由于回收AGU仅包括单个加法器，所以可以减少执行地址生成操作中通常需要的多次计算所需的硬件，而不会不利地影响性能。

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