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1. 发明申请

US20100259868A1 CHIP TYPE SOLID ELECTROLYTIC CAPACITOR 有权
标题翻译：芯片型固体电解电容器
公开(公告)号：US20100259868A1
公开(公告)日：2010-10-14
申请号：US12821568
申请日：2010-06-23
申请人： Tatsuo Fujii , Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
发明人： Tatsuo Fujii , Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
IPC分类号： H01G9/012
CPC分类号： H01G9/012 , H01G2/06 , H01G9/004 , H01G9/14 , H01G9/15
摘要： A chip type solid electrolytic capacitor includes a capacitor element-laminate. In the capacitor element-laminate, a plurality of capacitor elements, each having an anode portion and a cathode portion, are laminated so that the anode portions of the adjacent capacitor elements are disposed in the direction opposite to each other. Anode lead terminals are joined to the bottom faces of the anode portions of the capacitor elements disposed at both ends of the capacitor element-laminate. A cathode lead terminal is joined to the bottom face of the cathode portion of the capacitor element disposed in the center of the capacitor element-laminate. An Electrically insulating exterior resin coats the capacitor element-laminate so as to expose at least a part of the bottom faces of the anode lead terminals and a part of the cathode lead terminal.
摘要翻译：芯片型固体电解电容器包括电容器元件层叠体。在电容器元件层叠体中，层叠多个具有阳极部和阴极部的电容器元件，使得相邻的电容器元件的阳极部沿相反方向配置。阳极引线端子连接到设置在电容器元件 - 层叠体的两端的电容器元件的阳极部分的底面。阴极引线端子连接到设置在电容器元件 - 层叠体的中心的电容器元件的阴极部分的底面。电绝缘外部树脂涂覆电容器元件层压体，以暴露阳极引线端子和阴极引线端子的一部分的至少一部分底面。

2. 发明授权

US07778011B2 Chip type solid electrolytic capacitor 有权
标题翻译：片式固体电解电容器
公开(公告)号：US07778011B2
公开(公告)日：2010-08-17
申请号：US11719029
申请日：2006-01-19
申请人： Tatsuo Fujii , Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
发明人： Tatsuo Fujii , Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
IPC分类号： H01G9/00
CPC分类号： H01G9/012 , H01G2/06 , H01G9/004 , H01G9/14 , H01G9/15
摘要： A chip type solid electrolytic capacitor includes a capacitor element-laminate. In the capacitor element-laminate, a plurality of capacitor elements, each having an anode portion and a cathode portion, are laminated so that the anode portions of the adjacent capacitor elements are disposed in the direction opposite to each other. Anode lead terminals are joined to the bottom faces of the anode portions of the capacitor elements disposed at both ends of the capacitor element-laminate. A cathode lead terminal is joined to the bottom face of the cathode portion of the capacitor element disposed in the center of the capacitor element-laminate. An Electrically insulating exterior resin coats the capacitor element-laminate so as to expose at least a part of the bottom faces of the anode lead terminals and a part of the cathode lead terminal.
摘要翻译：芯片型固体电解电容器包括电容器元件层叠体。在电容器元件层叠体中，层叠多个具有阳极部和阴极部的电容器元件，使得相邻的电容器元件的阳极部沿相反方向配置。阳极引线端子连接到设置在电容器元件 - 层叠体的两端的电容器元件的阳极部分的底面。阴极引线端子连接到设置在电容器元件 - 层叠体的中心的电容器元件的阴极部分的底面。电绝缘外部树脂涂覆电容器元件层压体，以暴露阳极引线端子和阴极引线端子的一部分的至少一部分底面。

3. 发明授权

US07929273B2 Chip type solid electrolytic capacitor 有权
标题翻译：片式固体电解电容器
公开(公告)号：US07929273B2
公开(公告)日：2011-04-19
申请号：US12821568
申请日：2010-06-23
申请人： Tatsuo Fujii , Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
发明人： Tatsuo Fujii , Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
IPC分类号： H01G9/00
CPC分类号： H01G9/012 , H01G2/06 , H01G9/004 , H01G9/14 , H01G9/15
摘要： A chip type solid electrolytic capacitor includes a capacitor element-laminate. In the capacitor element-laminate, a plurality of capacitor elements, each having an anode portion and a cathode portion, are laminated so that the anode portions of the adjacent capacitor elements are disposed in the direction opposite to each other. Anode lead terminals are joined to the bottom faces of the anode portions of the capacitor elements disposed at both ends of the capacitor element-laminate. A cathode lead terminal is joined to the bottom face of the cathode portion of the capacitor element disposed in the center of the capacitor element-laminate. An Electrically insulating exterior resin coats the capacitor element-laminate so as to expose at least a part of the bottom faces of the anode lead terminals and a part of the cathode lead terminal.
摘要翻译：芯片型固体电解电容器包括电容器元件层叠体。在电容器元件层叠体中，层叠多个具有阳极部和阴极部的电容器元件，使得相邻的电容器元件的阳极部沿相反方向配置。阳极引线端子连接到设置在电容器元件 - 层叠体的两端的电容器元件的阳极部分的底面。阴极引线端子连接到设置在电容器元件 - 层叠体的中心的电容器元件的阴极部分的底面。电绝缘外部树脂涂覆电容器元件层压体，以暴露阳极引线端子和阴极引线端子的一部分的至少一部分底面。

4. 发明申请

US20090073638A1 CHIP TYPE SOLID ELECTROLYTIC CAPACITOR 有权
标题翻译：芯片型固体电解电容器
公开(公告)号：US20090073638A1
公开(公告)日：2009-03-19
申请号：US11719029
申请日：2006-01-19
申请人： Tatsuo Fujii , Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
发明人： Tatsuo Fujii , Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
IPC分类号： H01G9/15
CPC分类号： H01G9/012 , H01G2/06 , H01G9/004 , H01G9/14 , H01G9/15
摘要： A chip type solid electrolytic capacitor includes a capacitor element-laminate. In the capacitor element-laminate, a plurality of capacitor elements, each having an anode portion and a cathode portion, are laminated so that the anode portions of the adjacent capacitor elements are disposed in the direction opposite to each other. Anode lead terminals are joined to the bottom faces of the anode portions of the capacitor elements disposed at both ends of the capacitor element-laminate. A cathode lead terminal is joined to the bottom face of the cathode portion of the capacitor element disposed in the center of the capacitor element-laminate. An Electrically insulating exterior resin coats the capacitor element-laminate so as to expose at least a part of the bottom faces of the anode lead terminals and a part of the cathode lead terminal.
摘要翻译：芯片型固体电解电容器包括电容器元件层叠体。在电容器元件层叠体中，层叠多个具有阳极部和阴极部的电容器元件，使得相邻的电容器元件的阳极部沿相反方向配置。阳极引线端子连接到设置在电容器元件 - 层叠体的两端的电容器元件的阳极部分的底面。阴极引线端子连接到设置在电容器元件 - 层叠体的中心的电容器元件的阴极部分的底面。电绝缘外部树脂涂覆电容器元件层压体，以暴露阳极引线端子和阴极引线端子的一部分的至少一部分底面。

5. 发明授权

US07359180B2 Solid-state electrolytic capacitor and manufacturing method thereof 有权
标题翻译：固态电解电容器及其制造方法
公开(公告)号：US07359180B2
公开(公告)日：2008-04-15
申请号：US10595080
申请日：2005-04-11
申请人： Junichi Kurita , Kazuo Tadanobu , Kenji Kuranuki , Yuji Midou , Tsuyoshi Yoshino , Tatsuo Fujii , Hiroshi Serikawa
发明人： Junichi Kurita , Kazuo Tadanobu , Kenji Kuranuki , Yuji Midou , Tsuyoshi Yoshino , Tatsuo Fujii , Hiroshi Serikawa
IPC分类号： H01G9/04
CPC分类号： B60R16/027 , Y10T29/41 , Y10T29/417
摘要： A solid electrolytic capacitor includes a flat-shaped anode terminal having a first surface connected to an anode portion of a capacitor element and having a second surface opposite to the first surface, a flat-shaped cathode terminal having a first surface connected to a cathode layer of the capacitor element and having a second surface opposite to the first surface thereof, and an insulating resin package accommodating the capacitor element, the anode terminal, and the cathode terminal. The second surface of the cathode terminal is flush with the second surface of the anode terminal. The second surface of the anode terminal and the second surface of the cathode terminal expose to an outside of the resin package. The anode terminal includes a first thick portion and a first thin portion thinner than the first thick portion. The first thick portion has the second surface of the anode terminal and a portion of the first surface of the anode terminal. The first thin portion has a portion of the first surface of the anode terminal and being connected to the first thick portion. The cathode terminal includes a second thick portion and a second thin portion thinner than the second thick portion. The second thick portion has the second surface of the cathode terminal and a portion of the first surface of the cathode terminal. The second thin portion has a portion of the first surface and being connected to the second thick portion. This solid electrolytic capacitor has a small equivalent series inductance, and is stably mountable to a mount body.
摘要翻译：固体电解电容器包括平面状的阳极端子，其具有连接到电容器元件的阳极部分的第一表面并具有与第一表面相对的第二表面，扁平状阴极端子，其具有连接到阴极层的第一表面并且具有与其第一表面相对的第二表面，以及容纳电容器元件，阳极端子和阴极端子的绝缘树脂封装。阴极端子的第二表面与阳极端子的第二表面齐平。阳极端子的第二表面和阴极端子的第二表面暴露于树脂封装的外部。阳极端子包括第一厚部分和比第一厚部分更薄的第一薄部分。第一厚部具有阳极端子的第二表面和阳极端子的第一表面的一部分。第一薄部分具有阳极端子的第一表面的一部分并连接到第一厚部分。阴极端子包括第二厚部分和比第二厚部分更薄的第二薄部分。第二厚部具有阴极端子的第二表面和阴极端子的第一表面的一部分。第二薄部分具有第一表面的一部分并且连接到第二厚部分。该固体电解电容器具有小的等效串联电感，并且稳定地安装到安装体。

6. 发明授权

US07057882B2 Chip solid electrolytic capacitor 失效
标题翻译：芯片固体电解电容器
公开(公告)号：US07057882B2
公开(公告)日：2006-06-06
申请号：US11222964
申请日：2005-09-12
申请人： Tatsuo Fujii , Junichi Kurita , Yuji Midou , Tsuyoshi Yoshino
发明人： Tatsuo Fujii , Junichi Kurita , Yuji Midou , Tsuyoshi Yoshino
IPC分类号： H01G9/00 , H01G4/228 , H01G9/10
CPC分类号： H01G9/012 , H01G9/042 , H01G9/08 , H01G9/14
摘要： A chip solid electrolytic capacitor includes a capacitor element with an anode portion and a cathode portion, an anode lead frame, a cathode lead frame and packaging resin. The anode lead frame includes a first plane, an anode junction and an anode terminal. The anode junction is formed on one end of the first plane and connected to the anode portion. The anode terminal is formed on the other side of the first plane. The cathode lead frame has a second plane and a cathode terminal. The second plane has the cathode portion mounted thereon, is connected to the cathode portion, and is stacked on the first plane. The cathode terminal is formed on the same side of the second plane as the anode terminal. The packaging resin has a surface to be mounted and covers the capacitor element, with the anode terminal and the cathode terminal exposed on the surface to be mounted.
摘要翻译：芯片固体电解电容器包括具有阳极部分和阴极部分的电容器元件，阳极引线框架，阴极引线框架和封装树脂。阳极引线框架包括第一平面，阳极结和阳极端子。阳极结形成在第一平面的一端并连接到阳极部分。阳极端子形成在第一平面的另一侧上。阴极引线框架具有第二平面和阴极端子。第二平面具有安装在其上的阴极部分，连接到阴极部分，并且堆叠在第一平面上。阴极端子形成在与阳极端子相同的第二平面的一侧。包装树脂具有要安装的表面并且覆盖电容器元件，阳极端子和阴极端子暴露在要安装的表面上。

7. 发明申请

US20060056136A1 Chip solid electrolytic capacitor 失效
标题翻译：芯片固体电解电容器
公开(公告)号：US20060056136A1
公开(公告)日：2006-03-16
申请号：US11222964
申请日：2005-09-12
申请人： Tatsuo Fujii , Junichi Kurita , Yuji Midou , Tsuyoshi Yoshino
发明人： Tatsuo Fujii , Junichi Kurita , Yuji Midou , Tsuyoshi Yoshino
IPC分类号： H01G9/00
CPC分类号： H01G9/012 , H01G9/042 , H01G9/08 , H01G9/14
摘要： The chip solid electrolytic capacitor includes a capacitor element with an anode portion and a cathode portion, an anode lead frame, a cathode lead frame and packaging resin. The anode lead frame includes a first plane, an anode junction and an anode terminal. The anode junction is formed on one end of the first plane and connected to the anode portion. The anode terminal is formed on the other side of the first plane. The cathode lead frame has a second plane and a cathode terminal. The second plane mounts the cathode portion thereon and connected to the cathode portion, and is stacked on the first plane. The cathode terminal is formed on the same side of the second plane as the anode terminal. The packaging resin has a surface to be mounted and covers the capacitor element, with the anode terminal and the cathode terminal exposed on the surface to be mounted.
摘要翻译：芯片固体电解电容器包括具有阳极部分和阴极部分的电容器元件，阳极引线框架，阴极引线框架和封装树脂。阳极引线框架包括第一平面，阳极结和阳极端子。阳极结形成在第一平面的一端并连接到阳极部分。阳极端子形成在第一平面的另一侧上。阴极引线框架具有第二平面和阴极端子。第二平面将阴极部分安装在其上并连接到阴极部分，并且堆叠在第一平面上。阴极端子形成在与阳极端子相同的第二平面的一侧。包装树脂具有要安装的表面并且覆盖电容器元件，阳极端子和阴极端子暴露在要安装的表面上。

8. 发明授权

US07787234B2 Digital signal processor 有权
标题翻译：数字信号处理器
公开(公告)号：US07787234B2
公开(公告)日：2010-08-31
申请号：US11885458
申请日：2006-05-15
申请人： Hiroshi Serikawa , Kenji Kuranuki , Junichi Kurita , Tsuyoshi Yoshino , Katsuyuki Nakamura , Hiroshi Fujii
发明人： Hiroshi Serikawa , Kenji Kuranuki , Junichi Kurita , Tsuyoshi Yoshino , Katsuyuki Nakamura , Hiroshi Fujii
IPC分类号： H01G9/02
CPC分类号： H05K1/0231 , H01G4/35 , H01G9/012 , H01G9/10 , H01G9/15 , H01G9/28 , H05K2201/10689
摘要： A digital signal processor includes a component for processing a digital signal, a power line for supplying a power to the component, and a decoupling capacitor connected between the power line and a ground. The decoupling capacitor has an equivalent series resistance larger than zero and not larger than 25 mΩ at 100 kHz and an equivalent series inductance larger than zero and not larger than 800 pH at 500 MHz. This digital signal processor does not generate a lot of digital noise, and has a small, thin size.
摘要翻译：数字信号处理器包括用于处理数字信号的部件，用于向部件供电的电力线以及连接在电源线和地之间的去耦电容器。去耦电容器具有大于零且不大于25mΩ的等效串联电阻; 在100 kHz时，等效串联电感大于零，并且在500 MHz时不大于800 pH。该数字信号处理器不会产生大量的数字噪声，并且具有小而薄的尺寸。

9. 发明申请

US20060262487A1 Chip-type solid electrolytic capacitor 有权
标题翻译：片式固体电解电容器
公开(公告)号：US20060262487A1
公开(公告)日：2006-11-23
申请号：US11437666
申请日：2006-05-22
申请人： Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
发明人： Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
IPC分类号： H01G9/04
CPC分类号： H01G9/012 , H01G2/06 , H01G9/14 , Y10T29/41 , Y10T29/417
摘要： A chip-type solid electrolytic capacitor which has a four-terminal structure. The chip-type solid electrolytic capacitor includes capacitor elements laminated such that anode electrodes face alternately in opposite directions; a pair of anode terminals opposing to each other; and a pair of cathode terminals opposing to each other. The magnetic fluxes generated by current passing between respective terminals are mutually cancelled, thus allowing ESL to be drastically reduced. Further reduction of ESL is feasible by shortening the distance between the terminals as much as possible so as to reduce the current loop area.
摘要翻译：具有四端子结构的芯片型固体电解电容器。片式固体电解电容器包括电容器元件，其电容器元件层叠，使得阳极电极在相反方向上交替地面对一对阳极端子彼此相对; 和一对彼此相对的阴极端子。由相应端子之间的电流通过产生的磁通相互抵消，从而允许ESL被大大降低。通过尽可能地缩短端子之间的距离来进一步降低ESL是可行的，以便减小电流回路面积。

10. 发明授权

US07215533B2 Chip-type solid electrolytic capacitor 有权
标题翻译：片式固体电解电容器
公开(公告)号：US07215533B2
公开(公告)日：2007-05-08
申请号：US11437666
申请日：2006-05-22
申请人： Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
发明人： Junichi Kurita , Hiroshi Fujii , Tsuyoshi Yoshino
IPC分类号： H01G9/00
CPC分类号： H01G9/012 , H01G2/06 , H01G9/14 , Y10T29/41 , Y10T29/417
摘要： A chip-type solid electrolytic capacitor has a four-terminal structure. The chip-type solid electrolytic capacitor includes capacitor elements laminated such that anode electrodes face alternately in opposite directions; a pair of anode terminals opposing each other; and a pair of cathode terminals opposing each other. The magnetic fluxes generated by current passing between respective terminals are mutually cancelled, thus allowing ESL to be drastically reduced. Further reduction of ESL is feasible by shortening the distance between the terminals as much as possible so as to reduce the current loop area.
摘要翻译：芯片型固体电解电容器具有四端子结构。片式固体电解电容器包括电容器元件，其电容器元件层叠，使得阳极电极在相反方向上交替地面对一对阳极端子彼此相对; 和一对彼此相对的阴极端子。由相应端子之间的电流通过产生的磁通相互抵消，从而允许ESL被大大降低。通过尽可能地缩短端子之间的距离来进一步降低ESL是可行的，以便减小电流回路面积。

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