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1. 发明授权

US07973571B2 Multichannel drive circuit 失效
标题翻译：多通道驱动电路
公开(公告)号：US07973571B2
公开(公告)日：2011-07-05
申请号：US11660977
申请日：2006-11-20
申请人： Tatsumi Sato , Kazuhiko Maki , Toshiyuki Wada , Takamasa Yanai
发明人： Tatsumi Sato , Kazuhiko Maki , Toshiyuki Wada , Takamasa Yanai
IPC分类号： H03B1/00
CPC分类号： B41J2/45 , G09G3/3216 , G09G3/325 , G09G3/3283 , G09G3/3291 , G09G3/3607 , G09G3/3614 , G09G3/3685 , G09G3/3688 , G09G2300/0426 , G09G2300/06 , G09G2300/0842 , G09G2310/0248 , G09G2310/0272 , G09G2320/0223 , G09G2320/0233 , G09G2320/0242 , G09G2320/0276
摘要： The invention provides a multichannel drive circuit by which, even when there occurs a variation between channels in circuit characteristics of each channel including current source due to the semiconductor manufacturing process and the like, loads of each channel constituting a load array can be driven under conditions uniform between all the channels. The invention includes; an interchannel common connection line (5) for making conduction between respective current paths of each channel for connecting the respective current sources of each channel constituting a current source array (11) with respective input switches of each channel constituting an input switch array (13); and current blocking means (12) for blocking output current of the current source of that channel of the plurality of channels in which the input switch is in an OFF state from flowing into the interchannel common connection line.
摘要翻译：本发明提供一种多通道驱动电路，即使由于半导体制造工艺等而导致包括电流源在内的每个通道的电路特性的通道之间发生变化，也可以在条件下驱动构成负载阵列的每个通道的负载所有渠道之间均匀。本发明包括用于在每个通道的各个电流路径之间导通的通道间公共连接线（5），用于将构成电流源阵列（11）的每个通道的各个电流源与构成输入开关阵列（13）的每个通道的各个输入开关相连接， ; 以及用于阻止输入开关处于OFF状态的多个通道中的该通道的电流源的输出电流的电流阻塞装置（12）不流入通道间公共连接线。

2. 发明申请

US20090302898A1 MULTICHANNEL DRIVE CIRCUIT 失效
标题翻译：多通道驱动电路
公开(公告)号：US20090302898A1
公开(公告)日：2009-12-10
申请号：US11660977
申请日：2006-11-20
申请人： Tatsumi Sato , Kazuhiko Maki , Toshiyuki Wada , Takamasa Yanai
发明人： Tatsumi Sato , Kazuhiko Maki , Toshiyuki Wada , Takamasa Yanai
IPC分类号： G09G3/36
CPC分类号： B41J2/45 , G09G3/3216 , G09G3/325 , G09G3/3283 , G09G3/3291 , G09G3/3607 , G09G3/3614 , G09G3/3685 , G09G3/3688 , G09G2300/0426 , G09G2300/06 , G09G2300/0842 , G09G2310/0248 , G09G2310/0272 , G09G2320/0223 , G09G2320/0233 , G09G2320/0242 , G09G2320/0276
摘要： The invention provides a multichannel drive circuit by which, even when there occurs a variation between channels in circuit characteristics of each channel including current source due to the semiconductor manufacturing process and the like, loads of each channel constituting a load array can be driven under conditions uniform between all the channels. The invention includes; an interchannel common connection line (5) for making conduction between respective current paths of each channel for connecting the respective current sources of each channel constituting a current source array (11) with respective input switches of each channel constituting an input switch array (13); and current blocking means (12) for blocking output current of the current source of that channel of the plurality of channels in which the input switch is in an OFF state from flowing into the interchannel common connection line.
摘要翻译：本发明提供一种多通道驱动电路，即使由于半导体制造工艺等而导致包括电流源在内的每个通道的电路特性的通道之间发生变化，也可以在条件下驱动构成负载阵列的每个通道的负载所有渠道之间均匀。本发明包括用于在每个通道的各个电流路径之间导通的通道间公共连接线（5），用于将构成电流源阵列（11）的每个通道的各个电流源与构成输入开关阵列（13）的每个通道的各个输入开关相连接， ; 以及用于阻止输入开关处于OFF状态的多个通道中的该通道的电流源的输出电流的电流阻塞装置（12）不流入通道间公共连接线。

3. 发明授权

US5754814A Cache memory apparatus for reading data corresponding to input address information 失效
标题翻译：用于读取对应于输入地址信息的数据的高速缓存存储器
公开(公告)号：US5754814A
公开(公告)日：1998-05-19
申请号：US295685
申请日：1994-08-24
申请人： Kazuhiko Maki
发明人： Kazuhiko Maki
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0802 , G06F12/0859
摘要： A accordance determining circuit (113) that determines whether or not a cache address CA required in updating a cache data memory (111) and a cache tag memory (112) accords with the address of data read from an external memory (130) is provided. When the accordance determining circuit (150) has determined an accordance state, a register (115) is enabled so that cache data read from the external memory (130) is stored in a register (115) and supplied to a cache requester (101). Alternatively, a means for generating an address corresponding to the next data of data to be updated in updating the cache data memory (111) and (112) is provided so as to determine the cache status of an address being generated. Thus, if the determined result represents that the cache data has not been stored, a plurality of data are updated at a time. Consequently, the mis-hit penalty time can be reduced and the hit ratio can be improved.
摘要翻译： PCT No.PCT / JP93 / 00252 Sec。 371日期：1994年8月24日 102（e）日期1994年8月24日PCT 1993年3月1日PCT公布。公开号WO93 / 17386 日期1993年9月2日确定更新高速缓存数据存储器（111）和高速缓存标签存储器（112）所需的高速缓存地址CA是否符合从外部存储器读取的数据的地址的一致判定电路（113）（130）。当一致确定电路（150）确定了一致状态时，启用寄存器（115），使得从外部存储器（130）读取的高速缓存数据被存储在寄存器（115）中并提供给高速缓存请求器（101）。或者，提供用于在更新高速缓存数据存储器（111）和（112）时生成对应于要更新的数据的下一个数据的地址的装置，以便确定正在生成的地址的高速缓存状态。因此，如果确定的结果表示高速缓存数据尚未被存储，则一次更新多个数据。因此，可以减少误命中的惩罚时间，并且可以提高命中率。

4. 发明授权

US5634104A Cache memory apparatus for reading data corresponding to input address information 失效
标题翻译：用于读取对应于输入地址信息的数据的高速缓冲存储器装置
公开(公告)号：US5634104A
公开(公告)日：1997-05-27
申请号：US455029
申请日：1995-05-31
申请人： Kazuhiko Maki
发明人： Kazuhiko Maki
IPC分类号： G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F12/0888 , G06F12/0802 , G06F12/0859
摘要： A accordance determining circuit (113) that determines whether or not a cache address CA required in updating a cache data memory (111) and a cache tag memory (112) accords with the address of data read from an external memory (130) is provided. When the accordance determining circuit (150) has determined an accordance state, a register (115) is enabled so that cache data read from the external memory (130) is stored in a register (115) and supplied to a cache requester (101). Alternatively, a means for generating an address corresponding to the next data of data to be updated in updating the cache data memory (111) and (112) is provided so as to determine the cache status of an address being generated. Thus, if the determined result represents that the cache data has not been stored, a plurality of data are updated at a time. Consequently, the mis-hit penalty time can be reduced and the hit ratio can be improved.
摘要翻译：提供了确定在更新高速缓存数据存储器（111）和高速缓存标签存储器（112）中所需的高速缓存地址CA是否符合从外部存储器（130）读取的数据的地址的一致确定电路（113）。当一致确定电路（150）确定了一致状态时，启用寄存器（115），使得从外部存储器（130）读取的高速缓存数据被存储在寄存器（115）中并提供给高速缓存请求器（101）。或者，提供用于在更新高速缓存数据存储器（111）和（112）时生成对应于要更新的数据的下一个数据的地址的装置，以便确定正在生成的地址的高速缓存状态。因此，如果确定的结果表示高速缓存数据尚未被存储，则一次更新多个数据。因此，可以减少误命中的惩罚时间，并且可以提高命中率。

5. 发明授权

US5539874A Cache memory device for storing image data 失效
标题翻译：用于存储图像数据的缓存存储器件
公开(公告)号：US5539874A
公开(公告)日：1996-07-23
申请号：US529707
申请日：1995-09-18
申请人： Kazuhiko Maki , Eiji Komoto
发明人： Kazuhiko Maki , Eiji Komoto
IPC分类号： G06F12/08 , G06T1/60 , G09G5/393 , G06F12/06
CPC分类号： G09G5/393 , G06T1/60 , G06F12/0875
摘要： A cache memory device stores image data which are arranged corresponding to address data having first and second two-dimensional coordinate data. The image data are divided into a plurality of first groups in accordance with the first two-dimensional coordinate data, with the first groups further divided into a plurality of second groups in accordance with the second two-dimensional coordinate data. The cache memory device includes an image data memory for storing a given image data therein, which is divided into a plurality of block areas arranged in two dimensions. The reading and writing of image data from and to the image data memory is controlled by a central processing unit. A cache storage, comprising a cache memory, an address data decoding circuit, an address matching circuit and a control circuit, is coupled between the image data memory and the central processing unit by way of buses.
摘要翻译：高速缓冲存储器装置存储与具有第一和第二二维坐标数据的地址数据相对应的图像数据。根据第一二维坐标数据将图像数据分成多个第一组，根据第二二维坐标数据，第一组进一步分成多个第二组。高速缓冲存储器装置包括用于存储其中给定的图像数据的图像数据存储器，其被分成以二维布置的多个块区域。从图像数据存储器读取和写入图像数据由中央处理单元控制。包括高速缓冲存储器，地址数据解码电路，地址匹配电路和控制电路的高速缓存存储器通过总线耦合在图像数据存储器和中央处理单元之间。

6. 发明授权

US5307300A High speed processing unit 失效
标题翻译：高速处理单元
公开(公告)号：US5307300A
公开(公告)日：1994-04-26
申请号：US825976
申请日：1992-01-27
申请人： Eiji Komoto , Kazuhiko Maki
发明人： Eiji Komoto , Kazuhiko Maki
IPC分类号： G06F7/00 , G06F9/30 , G06F9/302 , G06F9/38 , G06F13/38 , G06F7/38
CPC分类号： G06F9/3001
摘要： A processing unit has a first data bus and a second data bus that receive first and second data from, respectively, first and second registers in a register file. An arithmetic-logic unit performs arithmetic and logic operations on the first and second data to produce third data, which it places on a third data bus. A selection circuit coupled to the first and third data buses selects either the first or third data for input to a third register in the register file, and either the first or third data for input to a fourth register in the register file. The first, second, third, and fourth registers are selected by a control circuit.
摘要翻译：处理单元具有从寄存器文件中的第一和第二寄存器分别接收第一和第二数据的第一数据总线和第二数据总线。算术逻辑单元对第一和第二数据执行算术和逻辑运算，以产生位于第三数据总线上的第三数据。耦合到第一和第三数据总线的选择电路选择用于输入到寄存器文件中的第三寄存器的第一或第三数据，以及用于输入到寄存器文件中的第四寄存器的第一或第三数据。第一，第二，第三和第四寄存器由控制电路选择。

7. 发明授权

US5893901A Text to voice apparatus accessing multiple gazetteers dependent upon vehicular position 失效
标题翻译：根据车辆位置对语音设备进行文本访问多个地名录
公开(公告)号：US5893901A
公开(公告)日：1999-04-13
申请号：US746340
申请日：1996-11-08
申请人： Kazuhiko Maki
发明人： Kazuhiko Maki
IPC分类号： G09B29/00 , G01C21/36 , G06F3/16 , G10L13/00 , G10L13/02 , G10L13/04 , G10L13/06 , G10L13/08 , G10L3/00
CPC分类号： G01C21/3629 , G10L13/027 , G10L13/047
摘要： An apparatus that changes text data into a voice signal based on the position of a vehicle is disclosed. A main gazetteer is subdivided into multiple area gazetteers, wherein each area gazetteer contains information corresponding to the mapping area that the vehicle is located. When the vehicle's position moves to a different mapping area, an analysis controller detects the change in mapping area and selects the new corresponding area gazetteer. The information of the new area gazetteer is then outputted as speech. This technique of subdividing the main gazetteer into area gazetteers increases the retrieval speed of information to the operator of the vehicle.
摘要翻译：公开了一种基于车辆位置将文本数据改变成语音信号的装置。主地名录被细分为多个区域地名词典，其中每个区域地名词典包含对应于车辆所在的映射区域的信息。当车辆的位置移动到不同的映射区域时，分析控制器检测映射区域的变化，并选择新的对应区域地名录。然后将新区域地名录的信息作为语音输出。将主要地名词典细分为区域地名词典的这种技术将信息的检索速度增加到车辆的操作者。

8. 发明授权

US5729707A Instruction prefetch circuit and cache device with branch detection 失效
标题翻译：指令预取电路和具有分支检测的缓存器件
公开(公告)号：US5729707A
公开(公告)日：1998-03-17
申请号：US539683
申请日：1995-10-05
申请人： Kazuhiko Maki
发明人： Kazuhiko Maki
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3804 , G06F9/3844
摘要： In an instruction prefetch circuit, even when a branch instruction is prefetched, the circuit continues a prefetch operation until branching is actually executed. Accordingly, when the branch instruction is a conditional branch instruction and not actually executed, the circuit continues the prefetch operation so that the prefetched instructions are efficiently supplied to a processor. It may be arranged that, when the branch instruction is an unconditional branch instruction, a branch destination address is extracted from the unconditional branch instruction and used as a prefetch address. Accordingly, the circuit continues the prefetch operation even when branching is executed. It may further be arranged that, when the branch instruction is a conditional branch instruction, a branch destination address is extracted from the conditional branch instruction and further a branch prediction is performed. When branching is expected based on the branch prediction, the branch destination address is used as a prefetch address. Accordingly, as long as the branch prediction does not fail, the circuit continues the prefetch operation.
摘要翻译：在指令预取电路中，即使当预取转移指令时，电路继续进行预取操作，直到实际执行分支。因此，当分支指令是条件转移指令而不是实际执行时，电路继续进行预取操作，使得预取指令被有效地提供给处理器。可以设置当分支指令是无条件转移指令时，从无条件转移指令中提取分支目的地地址并将其用作预取地址。因此，即使执行分支，电路也继续进行预取操作。另外，在分支指示为条件转移指令的情况下，从条件转移指令中提取分支目的地地址，进一步进行分支预测。当基于分支预测预期分支时，分支目的地地址被用作预取地址。因此，只要分支预测不失败，电路就继续进行预取操作。

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