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1. 发明申请

US20070138501A1 Semiconductor device and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070138501A1
公开(公告)日：2007-06-21
申请号：US11636656
申请日：2006-12-11
申请人： Taro Sugizaki , Motoaki Nakamura , Motonari Honda
发明人： Taro Sugizaki , Motoaki Nakamura , Motonari Honda
IPC分类号： H01L29/74
CPC分类号： H01L29/7436 , H01L29/7455
摘要： A semiconductor device has a thyristor including a first region of a first conduction type, a second region of a second conduction type opposite to the first conduction type, a third region of the first conduction type, and a fourth region of the second conduction type, in sequential junction, and has a gate electrode at the third region, wherein the second region is formed in a semiconductor substrate, and the first region is formed over the second region. A part of the region of a thyristor is thus provided with a laminate structure, whereby a reduction in element area can be achieved, and an enhanced punch-through resistance can be attained.
摘要翻译：半导体器件具有晶闸管，其包括第一导电类型的第一区域，与第一导电类型相反的第二导电类型的第二区域，第一导电类型的第三区域和第二导电类型的第四区域，并且在第三区域具有栅极电极，其中第二区域形成在半导体衬底中，并且第一区域形成在第二区域上。因此，晶闸管的一部分区域设置有层压结构，从而可以实现元件面积的减小，并且可以实现增强的穿通电阻。

2. 发明授权

US09136470B2 Memory element with ion conductor layer in which metal ions diffuse and memory device incorporating same 有权
标题翻译：具有离子导体层的记忆元件，其中金属离子扩散并且存储器件并入其中
公开(公告)号：US09136470B2
公开(公告)日：2015-09-15
申请号：US12957978
申请日：2010-12-01
申请人： Akihiro Maesaka , Kazuhiro Ohba , Tetsuya Mizuguchi , Koji Miyata , Motonari Honda , Katsuhisa Aratani
发明人： Akihiro Maesaka , Kazuhiro Ohba , Tetsuya Mizuguchi , Koji Miyata , Motonari Honda , Katsuhisa Aratani
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/085 , H01L27/2436 , H01L27/2472 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1608
摘要： The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.
摘要翻译：本发明提供了一种存储元件和存储器件，其实现了多个存储元件的初始状态或擦除状态下的电阻值的变化，并且能够将电阻值保持在写入/擦除状态以用于写入/擦除操作多次。存储元件按顺序包括第一电极，存储层和第二电极。存储层具有：包含碲（Te），硫（S）和硒（Se）的至少一种硫属元素的离子源层和至少一种选自铜（Cu），银（Ag），锌（Zn）和锆（Zr）; 以及具有比离子源层的电阻值高的电阻值并且具有不同组成的两个或更多个高电阻层。

3. 发明授权

US08693234B2 Memory unit and method of operating the same 有权
标题翻译：内存单元及其操作方法
公开(公告)号：US08693234B2
公开(公告)日：2014-04-08
申请号：US13363988
申请日：2012-02-01
申请人： Motonari Honda
发明人： Motonari Honda
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2013/0071 , G11C2013/0092 , G11C2213/56 , G11C2213/79
摘要： A memory unit includes memory elements and a drive section. In executing a first operation out of the first operation for changing resistance state of the memory element from one resistance state out of low resistance state and high resistance state to the other resistance state and a second operation for changing the resistance state of the memory element from the other resistance state to the one resistance state, the drive section performs stepwise operation, in which the drive section repeatedly performs, at least one time, a step in which strong stress application step for applying a stress for performing the first operation to the memory element as the drive target relatively strongly is performed and subsequently weak stress application step for applying a stress for performing the second operation to the memory element as the drive target relatively weakly is performed, and subsequently performs the strong stress application step.
摘要翻译：存储单元包括存储器元件和驱动部分。在从低电阻状态和高电阻状态的一个电阻状态到另一个电阻状态的用于将存储元件的电阻状态改变为第一操作的第一操作中执行第一操作和用于改变存储元件的电阻状态的第二操作至所述一个电阻状态的另一个电阻状态，所述驱动部执行逐步操作，其中所述驱动部至少一次重复执行将用于执行所述第一操作的应力的强应力施加步骤用于所述存储器的步骤执行相对强烈的作为驱动目标的元件，随后执行用于将作为执行第二操作的应力作为驱动目标相对较弱地施加到存储元件的弱应力施加步骤，并且随后执行强应力施加步骤。

4. 发明申请

US20120201069A1 MEMORY UNIT AND METHOD OF OPERATING THE SAME 有权
标题翻译：记忆单元及其操作方法
公开(公告)号：US20120201069A1
公开(公告)日：2012-08-09
申请号：US13363988
申请日：2012-02-01
申请人： Motonari Honda
发明人： Motonari Honda
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2013/0071 , G11C2013/0092 , G11C2213/56 , G11C2213/79
摘要： A memory unit includes memory elements and a drive section. In executing a first operation out of the first operation for changing resistance state of the memory element from one resistance state out of low resistance state and high resistance state to the other resistance state and a second operation for changing the resistance state of the memory element from the other resistance state to the one resistance state, the drive section performs stepwise operation, in which the drive section repeatedly performs, at least one time, a step in which strong stress application step for applying a stress for performing the first operation to the memory element as the drive target relatively strongly is performed and subsequently weak stress application step for applying a stress for performing the second operation to the memory element as the drive target relatively weakly is performed, and subsequently performs the strong stress application step.
摘要翻译：存储单元包括存储器元件和驱动部分。在从低电阻状态和高电阻状态的一个电阻状态到另一个电阻状态的用于将存储元件的电阻状态改变为第一操作的第一操作中执行第一操作和用于改变存储元件的电阻状态的第二操作至所述一个电阻状态的另一个电阻状态，所述驱动部执行逐步操作，其中所述驱动部至少一次重复执行将用于执行所述第一操作的应力的强应力施加步骤用于所述存储器的步骤执行相对强烈的作为驱动目标的元件，随后执行用于将作为执行第二操作的应力作为驱动目标相对较弱地施加到存储元件的弱应力施加步骤，并且随后执行强应力施加步骤。

5. 发明授权

US08519377B2 Nonvolatile memory device, nonvolatile memory device group, and manufacturing method thereof 有权
公开(公告)号：US08519377B2
公开(公告)日：2013-08-27
申请号：US13252643
申请日：2011-10-04
申请人： Jun Sumino , Motonari Honda
发明人： Jun Sumino , Motonari Honda
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L45/1246 , H01L27/228 , H01L27/2436 , H01L27/2472 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/085 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
摘要： A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.

6. 发明申请

US20120091415A1 NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE GROUP, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器件，非易失性存储器件组及其制造方法
公开(公告)号：US20120091415A1
公开(公告)日：2012-04-19
申请号：US13252643
申请日：2011-10-04
申请人： Jun Sumino , Motonari Honda
发明人： Jun Sumino , Motonari Honda
IPC分类号： H01L45/00 , H01L21/62
CPC分类号： H01L45/1246 , H01L27/228 , H01L27/2436 , H01L27/2472 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/085 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
摘要： A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.
摘要翻译：非易失性存储器件组包括：（A）第一绝缘层; （B）第二绝缘层，其具有与所述第一凹部连通的第一凹部和第二凹部，其宽度大于所述第一凹部的宽度，并且设置在所述第一绝缘层上; （C）多个电极，其设置在第一绝缘层中，其顶表面从第一凹部的底表面露出; （D）形成在第一凹部和第二凹部的侧壁和底表面上的信息存储层; 和（E）填充在由第二凹部中的信息存储层包围的空间中的导电材料层。

7. 发明申请

US20110140065A1 MEMORY ELEMENT AND MEMORY DEVICE 有权
标题翻译：存储元件和存储器件
公开(公告)号：US20110140065A1
公开(公告)日：2011-06-16
申请号：US12957978
申请日：2010-12-01
申请人： Akihiro Maesaka , Kazuhiro Ohba , Tetsuya Mizuguchi , Koji Miyata , Motonari Honda , Katsuhisa Aratani
发明人： Akihiro Maesaka , Kazuhiro Ohba , Tetsuya Mizuguchi , Koji Miyata , Motonari Honda , Katsuhisa Aratani
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , H01L27/2436 , H01L27/2472 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1608
摘要： The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.
摘要翻译：本发明提供了一种存储元件和存储器件，其实现了多个存储元件的初始状态或擦除状态下的电阻值的变化，并且能够将电阻值保持在写入/擦除状态以用于写入/擦除操作多次。存储元件按顺序包括第一电极，存储层和第二电极。存储层具有：包含碲（Te），硫（S）和硒（Se）的至少一种硫属元素的离子源层和至少一种选自铜（Cu），银（Ag），锌（Zn）和锆（Zr）; 以及具有比离子源层的电阻值高的电阻值并且具有不同组成的两个或更多个高电阻层。

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