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    • 1. 发明申请
    • Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
    • 处理器使用较少的硬件和指令转换设备减少指令类型的数量
    • US20050091478A1
    • 2005-04-28
    • US10617506
    • 2003-07-11
    • Shuichi TakayamaKensuke OdaniAkira TanakaNobuo HigakiMasato SuzukiTetsuya TanakaTaketo HeishiShinya Miyaji
    • Shuichi TakayamaKensuke OdaniAkira TanakaNobuo HigakiMasato SuzukiTetsuya TanakaTaketo HeishiShinya Miyaji
    • G06F9/30G06F9/318G06F9/32G06F9/38G06F9/45G06F9/00
    • G06F9/30058G06F8/447G06F9/30021G06F9/30072G06F9/30094G06F9/30145G06F9/30167G06F9/30181G06F9/3842
    • A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.
    • 解码并执行指令序列的处理器包括:状态保持单元,用于当执行预定指令时,保持所述预定指令的执行结果的更新状态; 获取单元,用于获得指令序列,所述指令序列由与分配给所述处理器的指令集的指令相匹配的指令组合,其中所述指令集被分配了第一条件指令;第一条件指令的第一状态条件与第二状态条件相互排斥, 第二条件指令,其具有与第一条件指令相同的操作码,指令集不被分配第二条件指令,以及指定一个状态和多个状态中的一个状态和多个状态的第一状态条件和第二状态条件; 解码单元,用于逐个地解码所获得的指令序列中的每个指令; 判断单元,用于当解码单元解码第一条件指令时,判断更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态; 以及执行单元,用于仅当判断单元的判断结果为肯定时,执行由解码单元解码的第一条件指令中由操作码指定的操作。
    • 2. 发明授权
    • Constant reconstruction processor that supports reductions in code size and processing time
    • 恒定重建处理器,支持缩小代码大小和处理时间
    • US06209080B1
    • 2001-03-27
    • US09124335
    • 1998-07-29
    • Taketo HeishiNobuo HigakiAkira TanakaTetsuya TanakaShuichi TakayamaKensuke OdaniShinya Miyaji
    • Taketo HeishiNobuo HigakiAkira TanakaTetsuya TanakaShuichi TakayamaKensuke OdaniShinya Miyaji
    • G06F930
    • G06F9/30167G06F9/30163G06F9/383G06F9/3853
    • A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361. When the decoding unit 20 finds that the instruction includes a branch operation, the execution unit 30 executes the branch operation using the constant stored in the branching constant register 362. When the decoding unit 20 finds that the instruction includes an arithmetic operation, the execution unit 30 executes the arithmetic operation using the constant stored in the operation constant register 361.
    • 用于基于指令执行操作的处理器包括操作常数寄存器361,分支常数寄存器362,用于解码存储在指令寄存器10中的指令的解码单元20,常数寄存器控制单元32和执行单元30.当 解码单元20发现指令包括要存储在分支常数寄存器362中的常数,常数寄存器控制单元32移位分支常数寄存器362中的当前值并插入要存储的常数,从而存储新常数 在分支常数寄存器362中。当解码单元20发现将常数存储在操作常数寄存器361中时,常数寄存器控制单元32移动操作常数寄存器361中的当前值,并插入要存储的常数 ,从而在操作常数寄存器361中存储新常数。当解码单元20发现指令包括时 分支操作,执行单元30使用存储在分支常数寄存器362中的常数来执行分支操作。当解码单元20发现指令包括算术运算时,执行单元30使用存储在 操作常数寄存器361。
    • 5. 发明授权
    • Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
    • 处理器使用较少的硬件和指令转换设备减少指令类型的数量
    • US06230258B1
    • 2001-05-08
    • US09144298
    • 1998-08-31
    • Shuichi TakayamaKensuke OdaniAkira TanakaNobuo HigakiMasato SuzukiTetsuya TanakaTaketo HeishiShinya Miyaji
    • Shuichi TakayamaKensuke OdaniAkira TanakaNobuo HigakiMasato SuzukiTetsuya TanakaTaketo HeishiShinya Miyaji
    • G06F930
    • G06F9/30058G06F8/447G06F9/30021G06F9/30072G06F9/30094G06F9/30145G06F9/30167G06F9/30181G06F9/3842
    • An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition. While the judgment unit decision is negative, the conversion unit converts the conversion target instruction sequence into an instruction sequence including a conditional instruction with a condition that is mutually exclusive with the predetemiined condition.
    • 一种用于将不包括条件指令的指令序列转换成包括条件指令的指令序列的指令转换装置和方法,其中条件指令包括当条件满足时由处理器执行的条件和操作代码两者。 获取单元接收不包括条件指令的指令序列,由此当满足预定条件时,指令序列检测单元检测到将不同转移对象传送到同一存储资源的转换目标指令序列。 判断单元判断专用处理器的指令集是否被分配条件指令,该条件指令包括与前提条件相同的条件,由此转换单元然后可以将转换目标指令序列转换为包括具有预定条件的条件指令的指令序列。 当判断单元判定为否定时,转换单元将转换目标指令序列转换成具有条件的条件指令的指令序列,该条件与预先设定的条件相互排斥。