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1. 发明申请

US20080307403A1 COMPILING APPARATUS 有权
标题翻译：编译器
公开(公告)号：US20080307403A1
公开(公告)日：2008-12-11
申请号：US12048401
申请日：2008-03-14
申请人： Taketo HEISHI , Shohei MICHIMOTO , Yukio IIMURA , Yasuhiro YAMAMOTO
发明人： Taketo HEISHI , Shohei MICHIMOTO , Yukio IIMURA , Yasuhiro YAMAMOTO
IPC分类号： G06F9/45 , G06F9/30
CPC分类号： G06F8/441
摘要： The present invention effectively utilizes auxiliary registers and provides a compiler system which secures error detectability when the auxiliary registers are shared for plural uses. The instruction definition resource configuring unit configures, as preparation for processing by the register assigning unit, respective resources such as a register to be defined or referred to by for each instruction in an intermediate code. The instruction definition resource configuring unit detects possibility of instructions each of which is to be decomposed into plural instructions. As for an instruction to be possibly decomposed, the instruction definition resource configuring unit configures a corresponding register in the intermediate code, assuming the corresponding register used for the decomposition to be defined and referred. The register assigning unit uses the register as a general register as far as a live range of the register used for the decomposition does not overlap.
摘要翻译：本发明有效地利用了辅助寄存器，并且提供了一种编译器系统，其在辅助寄存器被共享多个用途时确保了错误检测能力。指令定义资源配置单元配置为由寄存器分配单元进行处理的准备，对于中间代码中的每个指令要定义或引用的寄存器等各自的资源。指令定义资源配置单元检测将要分解成多个指令的指令的可能性。对于可能分解的指令，指令定义资源配置单元在中间代码中配置相应的寄存器，假定用于分解的相应寄存器被定义和引用。寄存器分配单元使用寄存器作为通用寄存器，只要用于分解的寄存器的实际范围不重叠。

2. 发明申请

US20070168984A1 COMPILING SYSTEM, DEBUGGING SYSTEM AND PROGRAM DEVELOPMENT SYSTEM 审中-公开
标题翻译：编译系统，调试系统和程序开发系统
公开(公告)号：US20070168984A1
公开(公告)日：2007-07-19
申请号：US11555449
申请日：2006-11-01
申请人： Taketo HEISHI , Ryoko MIYACHI , Shohei MICHIMOTO , Teruo KAWABATA , Yasuhiro YAMAMOTO
发明人： Taketo HEISHI , Ryoko MIYACHI , Shohei MICHIMOTO , Teruo KAWABATA , Yasuhiro YAMAMOTO
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/3628 , G06F8/443 , G06F8/51 , G06F11/3624
摘要： A compiling system which translates a source program written in a high-level language into a machine language program, and includes a source level optimizer which converts an original source S program into an optimized source program by optimizing the original source program at the source program level, a compiler which converts the optimized source program into the machine language program, and a final debug information selection generation unit which generates final debug information which indicates a corresponding relationship between the original source program and the machine language program.
摘要翻译：一种将以高级语言编写的源程序转换为机器语言程序的编译系统，其包括源级优化器，其通过在源程序级优化原始源程序将原始源S程序转换为优化的源程序将优化的源程序转换为机器语言程序的编译器，以及最终调试信息选择生成单元，生成表示原始源程序与机器语言程序的对应关系的最终调试信息。

3. 发明申请

US20060277529A1 COMPILER APPARATUS 有权
标题翻译：编译器
公开(公告)号：US20060277529A1
公开(公告)日：2006-12-07
申请号：US11420059
申请日：2006-05-24
申请人： Shohei MICHIMOTO , Taketo HEISHI , Hajime OGAWA , Teruo KAWABATA
发明人： Shohei MICHIMOTO , Taketo HEISHI , Hajime OGAWA , Teruo KAWABATA
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
摘要翻译：可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线中间程序，使数据依赖关系发生变化。

4. 发明申请

US20110252410A1 PROGRAM CONVERTING APPARATUS AND PROGRAM CONVERSION METHOD 有权
标题翻译：程序转换装置和程序转换方法
公开(公告)号：US20110252410A1
公开(公告)日：2011-10-13
申请号：US13163035
申请日：2011-06-17
申请人： Taketo HEISHI , Shohei MICHIMOTO , Teruo KAWABATA
发明人： Taketo HEISHI , Shohei MICHIMOTO , Teruo KAWABATA
IPC分类号： G06F9/45
CPC分类号： G06F8/445 , G06F8/314
摘要： A compiler, which corresponds to a recent processor having a multithread function, that enables execution of efficient instruction scheduling and allows a programmer to control the instruction scheduling includes: an instruction scheduling directive receiving unit which receives, from a programmer, a directive for specifying an instruction scheduling method; and an instruction scheduling unit which executes, conforming to one of instruction scheduling methods, instruction scheduling of rearranging intermediate codes corresponding to the source program. The instruction scheduling unit selects one of instruction scheduling methods according to the directive received by the instruction scheduling directive receiving unit, and executes instruction scheduling conforming to the selected instruction scheduling method.
摘要翻译：一种编译器，其对应于具有多线程功能的最近的处理器，其能够执行有效的指令调度并允许程序员控制指令调度包括：指令调度指令接收单元，其从程序员接收用于指定指令调度方法; 以及指令调度单元，其执行符合指令调度方法之一的重新排列与源程序对应的中间代码的指令调度。指令调度单元根据指令调度指示接收单元接收的指令选择指令调度方法之一，并执行符合所选指令调度方法的指令调度。

5. 发明申请

US20110276787A1 MULTITHREAD PROCESSOR, COMPILER APPARATUS, AND OPERATING SYSTEM APPARATUS 审中-公开
标题翻译：多功能处理器，编译器和操作系统设备
公开(公告)号：US20110276787A1
公开(公告)日：2011-11-10
申请号：US13186818
申请日：2011-07-20
申请人： Yoshihiro KOGA , Taketo HEISHI
发明人： Yoshihiro KOGA , Taketo HEISHI
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F8/45 , G06F9/3853
摘要： A multithread processor for executing, in parallel, instructions included in a plurality of threads includes: a calculating group including a plurality of calculators each of which is for executing an instruction; instruction grouping units which classify, for each thread, the instructions included in the thread into groups each of which includes instructions that are simultaneously executable by the calculators; a thread selecting unit which selects, per execution cycle of the multithread processor, a thread including instructions to be issued to the calculators, from among the threads, by controlling execution frequency for executing the instructions included in the threads; and an instruction issuing unit which issues, to the calculators, per execution cycle of the multithread processor, the instructions classified into each of the groups and being among the instructions included in the thread selected by the thread selecting unit.
摘要翻译：并行地执行包括在多个线程中的指令的多线程处理器包括：包括多个计算器的计算组，每个计算器用于执行指令; 指令分组单元，对于每个线程，将包括在线程中的指令分成组，每个指令包括可由计算器同时执行的指令; 线程选择单元，通过控制用于执行包括在线程中的指令的执行频率，从多线程处理器的每个执行周期中选择包括要发出到计算器的指令的线程; 以及指令发布单元，其向计算器发送分组到每个组中的指令，并且包括在由线程选择单元选择的线程中的指令之中的每个执行周期。

6. 发明申请

US20110078664A1 PROGRAM TRANSLATION METHOD AND NOTIFYING INSTRUCTION INSERTING METHOD 有权
标题翻译：程序翻译方法和通知指导插入方法
公开(公告)号：US20110078664A1
公开(公告)日：2011-03-31
申请号：US12962075
申请日：2010-12-07
申请人： Yoko MAKIYORI , Taketo HEISHI , Akira TAKUMA
发明人： Yoko MAKIYORI , Taketo HEISHI , Akira TAKUMA
IPC分类号： G06F9/44
CPC分类号： G06F8/41
摘要： The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions. According to this, the present invention enables analysis of the executed range in the program that includes the conditional instructions as well.
摘要翻译：本发明包括：转换步骤，用于将源程序转换为机器语言程序; 插入步骤，用于插入用于通知在程序语言程序中执行源程序的通知指令; 以及程序生成步骤，用于从其中插入通知指令的机器语言程序生成可执行程序。此外，在插入步骤中，通知指令被放置在构成机器语言程序的每个基本块的入口点，并且与条件指令组的条件相同的通知指令被放置在入口点的机器语言程序中提供的条件指令组。在程序生成步骤中，向通知指示的每一个授予用于识别通知指令的识别信息。据此，本发明还能够对包括条件指令的程序中的执行范围进行分析。

7. 发明申请

US20080295082A1 PROGRAM RE-WRITING APPARATUS 有权
标题翻译：程序重写设备
公开(公告)号：US20080295082A1
公开(公告)日：2008-11-27
申请号：US12107450
申请日：2008-04-22
申请人： Teruo KAWABATA , Masatsugu DAIMON , Taketo HEISHI , Hajime OGAWA
发明人： Teruo KAWABATA , Masatsugu DAIMON , Taketo HEISHI , Hajime OGAWA
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.
摘要翻译：一种程序重写方法，其将输入的程序重写到用于处理器的程序中，用于基于是或否执行标志来控制是否执行处理，所述程序重写方法包括：将比较处理插入到所输入的程序，比较第一地址信息的比较处理，第一地址信息是由包括在输入的程序中的第一存储器访问处理访问的存储器地址信息和作为包括第二存储器访问处理访问的存储器的地址信息的第二地址信息在输入的程序中，将比较结果写入是或否执行标志; 并且在输入的程序中插入“是”或“否”执行标志附加的逻辑保存处理，“是”或“否”执行标志附加的逻辑保存处理是基于“是”或“否”执行标志的值执行的处理，并且保持与执行时输入程序的结果。

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