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    • 3. 发明授权
    • Variable gain amplifier
    • 可变增益放大器
    • US06891405B2
    • 2005-05-10
    • US10191455
    • 2002-07-10
    • Kazuhiro FujimuraShinichi Tanabe
    • Kazuhiro FujimuraShinichi Tanabe
    • H03G3/10H03G1/00H03F3/45
    • H03G1/0023
    • The present invention provides systems and methods related to a variable gain amplifier. The variable gain amplifier includes a first differential amplifier, a second differential amplifier, a combining circuit, and a current control circuit. The first differential amplifier circuit and the second differential amplifier circuit share a common input signal and have different amplification degrees. Each of the first and second differential amplifier circuits includes a first transistor and a second transistor that form a differential pair. The first transistor and the second transistor of each differential amplifier circuit have bases that are supplied with the input signal, and collectors that output signals to the combining circuit. The current control circuit changes a ratio between a bias current of the first differential amplifier circuit and a bias current of said second differential amplifier circuit based on a gain control signal.
    • 本发明提供了与可变增益放大器相关的系统和方法。 可变增益放大器包括第一差分放大器,第二差分放大器,组合电路和电流控制电路。 第一差分放大器电路和第二差分放大器电路共用公共输入信号并具有不同的放大度。 第一和第二差分放大器电路中的每一个包括形成差分对的第一晶体管和第二晶体管。 每个差分放大器电路的第一晶体管和第二晶体管具有输入信号的基极和向组合电路输出信号的集电极。 电流控制电路基于增益控制信号改变第一差分放大器电路的偏置电流和所述第二差分放大器电路的偏置电流之间的比率。
    • 10. 发明申请
    • Semiconductor device and a method of manufacturing the same
    • 半导体装置及其制造方法
    • US20070246780A1
    • 2007-10-25
    • US11723344
    • 2007-03-19
    • Kozo WatanabeShoji YoshidaMasashi SaharaShinichi TanabeTakashi Hashimoto
    • Kozo WatanabeShoji YoshidaMasashi SaharaShinichi TanabeTakashi Hashimoto
    • H01L29/94H01L21/8234
    • H01L29/872H01L27/0629H01L28/20H01L29/7833
    • A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate. After a silicon nitride film is deposited over the substrate and an aperture reaching the substrate is formed by removing the silicon nitride-film and the silicon oxide film at the anode formation part of the Schottky barrier diode, a Ti film is deposited over the substrate including the inside of the aperture, and a TiSi2 layer which becomes an anode electrode of the Schottky-barrier diode is formed at the bottom of the aperture by applying a heat treatment to the substrate.
    • 提供了一种技术,其中可以在同一芯片中形成高性能肖特基势垒二极管和其他半导体元件,以控制步骤数量的增加。 在氧化硅膜沉积在其上形成n沟道型MISFET的衬底上并且选择性地去除栅电极和n + +型半导体区之上的氧化硅膜之后,沉积Co膜 并且通过对衬底进行热处理,在n + +型半导体区域和栅极上形成CoSi 2 +层。 在氮化硅膜沉积在衬底之上并且通过去除肖特基势垒二极管的阳极形成部分处的氮化硅膜和氧化硅膜来形成到达衬底的孔,在衬底上沉积Ti膜,包括 通过对基板进行热处理,在孔的底部形成孔径的内部和成为肖特基势垒二极管的阳极的TiSi 2层。