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1. 发明申请

US20160379144A1 INFORMATION PROCESSING SYSTEM AND FAILURE PREDICTION MODEL ADOPTION DETERMINING METHOD 审中-公开
标题翻译：信息处理系统和故障预测模型通过决策方法
公开(公告)号：US20160379144A1
公开(公告)日：2016-12-29
申请号：US15191731
申请日：2016-06-24
申请人： Satoshi MIZUNO , Takenori OKU , Hiroshi NISHIDA , Shunsuke HAYASHI , Kentaro SEO , Yusuke SHIBATA , Yuuta SANO , Takeyoshi SEKINE , Fumihiro NAGANO , Satoshi HATANAKA , Kenji UEDA
发明人： Satoshi MIZUNO , Takenori OKU , Hiroshi NISHIDA , Shunsuke HAYASHI , Kentaro SEO , Yusuke SHIBATA , Yuuta SANO , Takeyoshi SEKINE , Fumihiro NAGANO , Satoshi HATANAKA , Kenji UEDA
IPC分类号： G06Q10/06 , G06Q40/00
CPC分类号： G06Q10/0635 , G06Q10/067 , G06Q40/00
摘要： An information processing system includes at least one information processing apparatus. The information processing system includes a provisional cost calculator configured to apply failure history information to a failure prediction model to provisionally calculate a cost of the failure prediction model, the failure history information expressing failure history of at least one electronic device in which a failure has occurred, the failure prediction model including a symptom detection method for detecting a symptom of a failure to occur in the electronic device in association with a preventive action for preventing the failure to occur in the electronic device; and an adoption determiner configured to determine to adopt the failure prediction model by which a profit can be obtained, based on a result of the provisional calculation.
摘要翻译：信息处理系统包括至少一个信息处理装置。信息处理系统包括临时成本计算器，其被配置为将故障历史信息应用于故障预测模型以临时计算故障预测模型的成本，表示发生故障的至少一个电子设备的故障历史的故障历史信息所述故障预测模型包括与用于防止在所述电子设备中发生故障的预防动作相关联地检测所述电子设备中发生故障的症状的症状检测方法; 以及采用确定器，被配置为基于临时计算的结果来确定采用可以获得利润的故障预测模型。

2. 发明申请

US20160378584A1 INFORMATION PROCESSING SYSTEM AND FAILURE DIAGNOSIS METHOD 有权
标题翻译：信息处理系统和故障诊断方法
公开(公告)号：US20160378584A1
公开(公告)日：2016-12-29
申请号：US15191705
申请日：2016-06-24
申请人： Takenori OKU , Hiroshi NISHIDA , Kentaro SEO , Shunsuke HAYASHI , Yusuke SHIBATA , Yuuta SANO , Satoshi MIZUNO , Takeyoshi SEKINE , Fumihiro NAGANO , Satoshi HATANAKA , Kenji UEDA
发明人： Takenori OKU , Hiroshi NISHIDA , Kentaro SEO , Shunsuke HAYASHI , Yusuke SHIBATA , Yuuta SANO , Satoshi MIZUNO , Takeyoshi SEKINE , Fumihiro NAGANO , Satoshi HATANAKA , Kenji UEDA
IPC分类号： G06F11/07 , H04N1/00 , G06F3/12
CPC分类号： G06F11/079 , G06F11/0733 , G06F11/0793 , H04N1/00015 , H04N1/00029 , H04N1/00039 , H04N1/00061 , H04N1/00079
摘要： An information processing system includes a storage unit that stores and associates a cause of a failure that has occurred in an electronic device, state information of the electronic device at the time the failure has occurred in the electronic device due to the cause of the failure, and a measure to be implemented in response to the cause of the failure. The information processing system further includes at least one processor that performs an acquisition process for acquiring the state information of the electronic device, and a failure diagnosis process for determining the cause of the failure that has occurred in the electronic device and the measure to be implemented in response to the cause of the failure based on the acquired state information of the electronic device.
摘要翻译：信息处理系统包括存储单元，其存储和关联在电子设备中发生的故障的原因，由于故障原因在电子设备中发生故障时的电子设备的状态信息，以及为应对失败原因而采取的措施。信息处理系统还包括执行用于获取电子设备的状态信息的获取过程的至少一个处理器，以及用于确定电子设备中发生的故障原因的故障诊断处理和要实现的措施响应于基于所获取的电子设备的状态信息的故障原因。

3. 发明申请

US20120106254A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20120106254A1
公开(公告)日：2012-05-03
申请号：US13235390
申请日：2011-09-18
申请人： Yuuta SANO , Toshifumi Watanabe
发明人： Yuuta SANO , Toshifumi Watanabe
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/26 , G11C16/32
摘要： According to one embodiment, a memory system includes a NAND flash memory, a first unit, and an second unit. Memory cells capable of holding data and management data as a first control signal. Memory cells are arranged in a matrix in the NAND flash memory. The first unit holds a second and a third signal. The second signal is made variable in accordance with an output frequency. The third signal is made variable. The second unit outputs the data to an outside in accordance with the first to third signals. The second unit includes a buffer unit including first to third transistors. The output frequency includes a first frequency and a second frequency. If the first to third transistors output the data to the outside in synchronization with the second frequency, the first to third transistors may be turned on regardless of a value of the first control signal.
摘要翻译：根据一个实施例，存储器系统包括NAND快闪存储器，第一单元和第二单元。能够将数据和管理数据保存为第一控制信号的存储单元。存储器单元被布置在NAND闪存中的矩阵中。第一单元保持第二和第三信号。第二信号根据输出频率变化。第三个信号是可变的。第二单元根据第一至第三信号将数据输出到外部。第二单元包括包括第一至第三晶体管的缓冲单元。输出频率包括第一频率和第二频率。如果第一至第三晶体管与第二频率同步地将数据输出到外部，则不管第一控制信号的值如何，第一至第三晶体管可以导通。

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