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1. 发明授权

US07436759B2 Reception apparatus and method, and channel response measurement apparatus for receiving an orthogonal frequency divisional multiplexing signal 有权
标题翻译：接收装置和方法以及用于接收正交频分复用信号的信道响应测量装置
公开(公告)号：US07436759B2
公开(公告)日：2008-10-14
申请号：US10514818
申请日：2003-05-16
申请人： Takaya Hayashi , Kenichiro Hayashi , Takehiro Kamada
发明人： Takaya Hayashi , Kenichiro Hayashi , Takehiro Kamada
IPC分类号： H04J11/00 , H04J1/00 , H04L7/04
CPC分类号： H04L25/0222 , H04L5/0048 , H04L25/022 , H04L25/0232 , H04L25/03159 , H04L27/2647
摘要： A reception apparatus for receiving an OFDM signal having a plurality of pilot carriers that transmit predetermined pilot signals at predetermined symbols. The reception apparatus transforms the received OFDM signal to a frequency-domain OFDM signal, determines channel responses corresponding to the transmitted pilot signals for each of the pilot carriers among a plurality of carriers constituting the frequency-domain OFDM signal, determines, based on channel responses corresponding to first, second and third pilot signals transmitted sequentially in a same carrier, a channel response at a symbol between the second pilot signal and the third pilot signal, compensates a waveform distortion in the frequency-domain OFDM signal according to the channel response at the symbol between the second pilot signal and the third pilot signal and outputs the results.
摘要翻译：一种用于接收具有以预定符号发送预定导频信号的多个导频载波的OFDM信号的接收装置。接收装置将接收的OFDM信号变换为频域OFDM信号，根据信道响应确定构成频域OFDM信号的多个载波中的每个导频载波对应于所发送的导频信号的信道响应对应于在相同载波中顺序发送的第一，第二和第三导频信号，在第二导频信号和第三导频信号之间的符号处的信道响应，根据信道响应在频域OFDM信号中补偿波形失真第二导频信号和第三导频信号之间的符号，并输出结果。

2. 发明授权

US06738949B2 Error correction circuit and error correction method 有权
标题翻译：纠错电路和纠错方法
公开(公告)号：US06738949B2
公开(公告)日：2004-05-18
申请号：US09311394
申请日：1999-05-13
申请人： Hiroyuki Senda , Akira Kisoda , Takehiro Kamada
发明人： Hiroyuki Senda , Akira Kisoda , Takehiro Kamada
IPC分类号： H03M1303
CPC分类号： H03M13/6325 , H03M13/23 , H03M13/256 , H03M13/2707 , H03M13/2933 , H03M13/2936 , H03M13/3961 , H03M13/41 , H03M13/4169 , H03M13/4192 , H03M13/6362 , H03M13/6502 , H03M13/6505
摘要： The present invention provides an error correction circuit for receiving and decoding a trellis-encoded signal of a series of data Zq, Zq−1, . . . ,Z1 which comprises convolutional-encoded bits and unencoded bits, the convolutional-encoded bits being obtained by convolutional-encoding lower t bits Xt, Xt−1, . . . ,X1 of an input p-bit series of data Xp, Xp−1, . . . , X1 (where p≧2, q≧p, and p>t≧1), and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The circuit includes: a maximum likelihood decoder for preselecting one of m parallel paths of transition from state x at time k to state y at time k+1.
摘要翻译：本发明提供一种用于接收和解码一系列数据Zq，Zq-1的网格编码信号的纠错电路。。。 Z1，其包括卷积编码比特和未编码比特，卷积编码比特是通过卷积编码较低T比特Xt，Xt-1获得的。。。，输入p位数据系列Xp，Xp-1，的X1。。。，X1（其中p> = 2，q> = p和p> t> = 1），并且未经编码的比特是通过不对其上（p-t）比特进行卷积编码而获得的。该电路包括：最大似然解码器，用于预先选择从时刻k的状态x到时间k + 1处的状态y的m个并行路径中的一个。

3. 发明授权

US06647530B1 Apparatus and method for viterbi decoding 有权
标题翻译：维特比解码的装置和方法
公开(公告)号：US06647530B1
公开(公告)日：2003-11-11
申请号：US09719434
申请日：2000-12-12
申请人： Takehiro Kamada
发明人： Takehiro Kamada
IPC分类号： H03M1341
CPC分类号： H03M13/6502 , H03M13/4107 , H03M13/4169
摘要： The path temporary storage unit 101 stores path select signals outputted from the ACS means 100 over a certain period of time. The partial trace back unit 102 performs a partial trace back between the first time point and the second time point by using the path select signals stored in the path temporary storage unit 101, and detects a non-passing node through which surviving paths do not pass at the second time point. The conversion unit 103 receives the signals from the partial trace back unit 102, and converts the path select signal corresponding to the non-passing node into a predetermined fixed value. This decreases the probability of occurrence of a signal transition in the path memory 104, thereby reducing power consumption.
摘要翻译：路径临时存储单元101在一段时间内存储从ACS装置100输出的路径选择信号。部分追溯单元102通过使用存储在路径临时存储单元101中的路径选择信号来执行在第一时间点和第二时间点之间的部分回溯，并且检测不经过的路径不通过的不通过节点在第二时间点。转换单元103从部分跟踪返回单元102接收信号，并将与非传递节点相对应的路径选择信号转换成预定的固定值。这降低了路径存储器104中的信号转换的发生概率，从而降低功耗。

4. 发明授权

US5450415A Boundary scan cell circuit and boundary scan test circuit 失效
标题翻译：边界扫描单元电路和边界扫描测试电路
公开(公告)号：US5450415A
公开(公告)日：1995-09-12
申请号：US155168
申请日：1993-11-19
申请人： Takehiro Kamada
发明人： Takehiro Kamada
IPC分类号： G01R31/317 , G01R31/3185 , H04B17/00
CPC分类号： G01R31/318547 , G01R31/31701
摘要： The invention discloses a boundary scan cell circuit for use in checking a wire, establishing a connection between the output pin of one IC and the input pin of the other IC, for stuck-at "0"/"1" faults. In an input boundary scan cell circuit in connection with the input pin, a third selector, in response to a control signal, selects one of a signal from a logic signal input terminal and an XOR from an arithmetic unit thereby outputting a signal thus selected. The output of the third selector is latched by a first flip-flop. The arithmetic unit performs the XOR addition of the output of the first flip-flop and the value of a logic signal from the logic signal input terminal. The result of the XOR addition is scanned-out at a scan signal output terminal. This reduces the number of shift operation cycles required for scan-out of the test result thereby shortening the time taken for testing. In an output boundary scan cell circuit, test data is automatically logic-inverted, so that no shift operation cycles necessary for scan-in of inverted test data are required. Therefore, this reduces the time taken for testing.
摘要翻译：本发明公开了一种用于检查导线的边界扫描单元电路，建立了一个IC的输出引脚与另一个IC的输入引脚之间的连接，用于卡住“0”/“1”故障。在与输入引脚相关的输入边界扫描单元电路中，响应于控制信号的第三选择器从逻辑信号输入端选择一个信号和从运算单元选择XOR，从而输出这样选择的信号。第三选择器的输出由第一触发器锁存。算术单元执行第一触发器的输出的XOR加法和来自逻辑信号输入端的逻辑信号的值。 XOR加法的结果在扫描信号输出端被扫描。这减少了扫描出测试结果所需的换档操作次数，从而缩短了测试所需的时间。在输出边界扫描单元电路中，测试数据被自动逻辑反相，因此不需要对反向测试数据进行扫描所需的移位操作周期。因此，这样可以减少测试所需的时间。

5. 发明授权

US07861146B2 Viterbi decoding apparatus and Viterbi decoding method 有权
标题翻译：维特比解码装置和维特比解码方法
公开(公告)号：US07861146B2
公开(公告)日：2010-12-28
申请号：US11597541
申请日：2005-02-16
申请人： Kouya Watanabe , Takehiro Kamada
发明人： Kouya Watanabe , Takehiro Kamada
IPC分类号： H03M13/41
CPC分类号： H03M13/3994 , H03M13/4176
摘要： In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit (103) detects a termination timing of a Viterbi code, a compulsion generation unit (105) generates a compulsion value so as to pass a specific path at the termination timing and timings before and after the termination timing, and the compulsion value is set on a traceback pointer (106). Therefore, even when the decoding state of a code before termination is degraded, decoding of a next code can be carried out without being affected by the degradation, thereby improving error correcting capability.
摘要翻译：在维特比解码装置中，控制终止码之前和之后的纠错能力的恶化。终端定时检测单元（103）检测维特比码的终止定时，强制生成单元（105）产生强制值，以便在终止定时和终止定时之前和之后的定时通过特定路径，并且强制值设置在回溯指针（106）上。因此，即使当终止之前的代码的解码状态劣化时，也可以不影响劣化地执行下一个代码的解码，从而提高纠错能力。

6. 发明授权

US6041433A Viterbi decoder and viterbi decoding method 失效
标题翻译：维特比解码器和维特比解码方法
公开(公告)号：US6041433A
公开(公告)日：2000-03-21
申请号：US833483
申请日：1997-04-07
申请人： Takehiro Kamada
发明人： Takehiro Kamada
IPC分类号： H03M13/23 , H03M13/41 , H03M13/00 , H03M13/12
CPC分类号： H03M13/6502 , H03M13/4107 , H03M13/4169 , H03M13/6505
摘要： The present invention provides an improved Viterbi decoder with a trace-back memory that requires a much less storage capacity required for signal decoding processing as compared with a commonly-used trace-back memory. Based on an input received code, an add-compare-select (ACS) circuit generates path select (PS) signals, and m generated PS signals per unit are written into a path storing means and are fed to a starting node number deciding circuit where the number m indicates a trace-back length. The starting node number deciding circuit finds from the m PS signals a trace-back starting node number for a PS signal preceding the m PS signals. PS signals are read out from the path storing means, trace-back processing starts from the starting node number found by the starting node number deciding circuit, and signal decoding processing is carried out. This eliminates the need for providing a state of performing provisional trace-back processing for finding a starting node number, thereby reducing the number of states necessary for the decoding of signals from four down to three. This reduces the storage capacity of memory required for storing PS signals and thereby achieves a considerable reduction of the circuit size.
摘要翻译：本发明提供了一种具有追溯存储器的改进的维特比解码器，其与常用的追溯存储器相比需要比信号解码处理所需的更少的存储容量。基于输入接收码，加法比较选择（ACS）电路产生路径选择（PS）信号，并且每单位的m个生成的PS信号被写入路径存储装置，并被馈送到起始节点号决定电路，其中数字m表示追溯长度。起始节点号决定电路从m PS信号中找出用于m PS信号之前的PS信号的追溯起始节点号。从路径存储装置读出PS信号，从起始节点号决定电路所发现的起始节点编号开始追踪处理，进行信号解码处理。这消除了提供执行用于查找起始节点号码的临时追溯处理的状态的需要，从而减少了信号从4个到3个解码所需的状态数量。这降低了存储PS信号所需的存储器的存储容量，从而实现了电路尺寸的显着降低。

7. 发明授权

US5621740A Output pad circuit for detecting short faults in integrated circuits 失效
标题翻译：用于检测集成电路中短路故障的输出焊盘电路
公开(公告)号：US5621740A
公开(公告)日：1997-04-15
申请号：US242673
申请日：1994-05-13
申请人： Takehiro Kamada
发明人： Takehiro Kamada
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318572 , G01R31/31855
摘要： Provided with an integrated circuit are plural output pad circuits being connected to wires by way of an output pin. Each output pad circuit comprises an input section for taking in an external test signal; a generator, connected to an output of the input section, for generating a signal whose logic value is the same as the logic value of a signal from the input section; a controller for controlling the generator; and a measurement section for measuring the logic value of a signal from the generator. The controller controls the generator in order that a logic 1 signal and a logic 0 signal generated by the generator have different electric current levels in the test operation mode. If there occurs a short between a wire being connected to an output pad circuit that receives a logic 1 signal and a wire being connected to an output pad circuit that receives a logic 0 signal, then signals from these output pad circuits will have the logic value of one of the logic 1 signal and the logic 0 signal that has a higher electric current level than the other. On the other hand, in the normal operation mode, the generator generates both a logic 1 signal and a logic 0 signal at the same electric current level so as to balance the electric current level.
摘要翻译：具有集成电路的多个输出焊盘电路通过输出引脚连接到电线。每个输出焊盘电路包括用于接收外部测试信号的输入部分; 连接到输入部分的输出的发生器，用于产生逻辑值与来自输入部分的信号的逻辑值相同的信号; 用于控制发电机的控制器; 以及用于测量来自发电机的信号的逻辑值的测量部分。控制器控制发生器，使得发生器产生的逻辑1信号和逻辑0信号在测试操作模式下具有不同的电流水平。如果在连接到接收逻辑1信号的输出焊盘电路的电线与连接到接收逻辑0信号的输出焊盘电路的电线之间发生短路，则来自这些输出焊盘电路的信号将具有逻辑值逻辑1信号和逻辑0信号之一具有比另一个更高的电流电平。另一方面，在正常工作模式中，发电机产生相同电流电平的逻辑1信号和逻辑0信号，以平衡电流电平。

8. 发明申请

US20070234190A1 Viterbi Decoding Apparatus and Viterbi Decoding Method 有权
标题翻译：维特比解码装置和维特比译码方法
公开(公告)号：US20070234190A1
公开(公告)日：2007-10-04
申请号：US11597541
申请日：2005-02-16
申请人： Kouya Watanabe , Takehiro Kamada
发明人： Kouya Watanabe , Takehiro Kamada
IPC分类号： H03M13/41
CPC分类号： H03M13/3994 , H03M13/4176
摘要： In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit (103) detects a termination timing of a Viterbi code, a compulsion generation unit (105) generates a compulsion value so as to pass a specific path at the termination timing and timings before and after the termination timing, and the compulsion value is set on a traceback pointer (106). Therefore, even when the decoding state of a code before termination is degraded, decoding of a next code can be carried out without being affected by the degradation, thereby improving error correcting capability.
摘要翻译：在维特比解码装置中，控制终止码之前和之后的纠错能力的恶化。终端定时检测单元（103）检测维特比码的终止定时，强制生成单元（105）产生强制值，以便在终止定时和终止定时之前和之后的定时通过特定路径，并且强制值设置在回溯指针（106）上。因此，即使当终止之前的代码的解码状态劣化时，也可以不影响劣化地执行下一个代码的解码，从而提高纠错能力。

9. 发明授权

US06728926B1 Encoding rate detection method and encoding rate detection device 失效
标题翻译：编码率检测方法和编码速率检测装置
公开(公告)号：US06728926B1
公开(公告)日：2004-04-27
申请号：US09831636
申请日：2001-05-11
申请人： Takashi Kakemizu , Takehiro Kamada , Yuji Nakai
发明人： Takashi Kakemizu , Takehiro Kamada , Yuji Nakai
IPC分类号： H03M1300
CPC分类号： H03M13/33 , H03M13/01 , H04L1/0046 , H04L7/041
摘要： In accordance with a rate detecting method for detecting a predetermined rate at which a received signal has been coded, the coded signal is decoded based on a first synchronizing signal having a frequency corresponding to a first rate such that a first decoded signal (ST11) is generated and then it is judged whether or not synchronization is determined for the first decoded signal (ST12). If the synchronization cannot be determined, there is generated only a second synchronizing signal having a frequency corresponding to a second rate having a difference between itself and a first rate which is smaller than a permissible value of the rate determined by the lower and upper values of the rate (ST13, ST17).
摘要翻译：根据用于检测接收信号已被编码的预定速率的速率检测方法，基于具有与第一速率对应的频率的第一同步信号来解码编码信号，使得第一解码信号（ST11）为然后判断是否确定了第一解码信号的同步（ST12）。如果不能确定同步，则只产生第二同步信号，该第二同步信号具有对应于第二速率的频率，该第二速率具有自身与第一速率之间的差值，该第一速率小于由下限和下限值确定的速率的允许值率（ST13，ST17）。

10. 发明授权

US5671233A Integrated circuit incorporating a test circuit 失效
标题翻译：集成电路并入测试电路
公开(公告)号：US5671233A
公开(公告)日：1997-09-23
申请号：US646564
申请日：1996-05-08
申请人： Takehiro Kamada
发明人： Takehiro Kamada
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/31855
摘要： Disposed in an integrated circuit is a test circuit having: a plurality of tristate buffers each for supplying, in a test mode, a charging current to a stray capacitance of a corresponding wire on a printed circuit board through a corresponding signal terminal of the integrated circuit; and a plurality of exclusive-OR gates each for supplying a logical signal having a pulse width indicative of a time interval between an input transition time and an output transition time of a corresponding tristate buffer. A difference in capacitance between a state where a signal terminal is being properly electrically connected to a wire on the printed circuit board and a state where the signal terminal is being improperly electrically connected thereto, is converted into a difference in pulse width of a logical signal, based on which a defective soldering of open failure in the signal terminal is detected.
摘要翻译：在集成电路中设置的测试电路具有：多个三态缓冲器，每个三态缓冲器用于在测试模式中通过集成电路的相应信号端将充电电流提供给印刷电路板上相应导线的杂散电容 ; 以及多个异或门，每个异或门用于提供具有指示相应三态缓冲器的输入转变时间和输出转换时间之间的时间间隔的脉冲宽度的逻辑信号。信号端子正确地电连接到印刷电路板上的导线的状态与信号端子不正确地电连接的状态之间的电容差被转换成逻辑信号的脉冲宽度差基于此，检测到信号端子中的开路故障的焊接不良。

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