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1. 发明授权

US07248529B2 Semiconductor device having fuse and its manufacture method 有权
标题翻译：具有保险丝的半导体器件及其制造方法
公开(公告)号：US07248529B2
公开(公告)日：2007-07-24
申请号：US10935426
申请日：2004-09-08
申请人： Takayuki Kamiya , Masayoshi Omura
发明人： Takayuki Kamiya , Masayoshi Omura
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has: a fuse having one end applied with a first voltage, and a MOS transistor having source, gate and drain and a connection point between the other end of the fuse and one of the source and drain, a second voltage lower than the first voltage applied to the other of the source and drain, wherein: the first and second voltages, characteristics of the MOS transistor and a resistance of the fuse are selected so that the fuse can be broken down when a predetermined program voltage is applied to the gate; and the resistance of the fuse is set to such a value as a voltage difference between a voltage at the connection point and the second voltage is lower than a drain voltage of the MOS transistor at which a drain current starts saturating, when the program voltage is applied to the gate.
摘要翻译：半导体器件具有：具有施加第一电压的一端的熔丝和具有源极，栅极和漏极的MOS晶体管以及熔丝另一端与源极和漏极中的一个之间的连接点，第二电压低于施加到源极和漏极中的另一个的第一电压，其中：选择第一和第二电压，MOS晶体管的特性和熔丝的电阻，使得当将预定的编程电压施加到大门; 并且熔断器的电阻被设定为如下值：当连接点和第二电压之间的电压差低于漏极电流开始饱和的MOS晶体管的漏极电压时，当编程电压为应用于门。

2. 发明授权

US06804159B2 Semiconductor device having fuse and its manufacture method 有权
标题翻译：具有保险丝的半导体器件及其制造方法
公开(公告)号：US06804159B2
公开(公告)日：2004-10-12
申请号：US10288493
申请日：2002-11-06
申请人： Takayuki Kamiya , Masayoshi Omura
发明人： Takayuki Kamiya , Masayoshi Omura
IPC分类号： G11C700
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has: a fuse having one end applied with a first voltage, and a MOS transistor having source, gate and drain and a connection point between the other end of the fuse and one of the source and drain, a second voltage lower than the first voltage applied to the other of the source and drain, wherein: the first and second voltages, characteristics of the MOS transistor and a resistance of the fuse are selected so that the fuse can be broken down when a predetermined program voltage is applied to the gate; and the resistance of the fuse is set to such a value as a voltage difference between a voltage at the connection point and the second voltage is lower than a drain voltage of the MOS transistor at which a drain current starts saturating, when the program voltage is applied to the gate.
摘要翻译：半导体器件具有：具有施加第一电压的一端的熔丝和具有源极，栅极和漏极的MOS晶体管以及熔丝另一端与源极和漏极中的一个之间的连接点，第二电压低于施加到源极和漏极中的另一个的第一电压，其中：选择第一和第二电压，MOS晶体管的特性和熔丝的电阻，使得当将预定的编程电压施加到大门; 并且熔断器的电阻被设定为如下值：当连接点和第二电压之间的电压差低于漏极电流开始饱和的MOS晶体管的漏极电压时，当编程电压为应用于门。

3. 发明申请

US20050099860A1 Method of breaking down a fuse in a semiconductor device 有权
标题翻译：分解半导体器件中的保险丝的方法
公开(公告)号：US20050099860A1
公开(公告)日：2005-05-12
申请号：US11015030
申请日：2004-12-20
申请人： Takayuki Kamiya , Masayoshi Omura
发明人： Takayuki Kamiya , Masayoshi Omura
IPC分类号： H01L21/82 , H01L23/525 , G11C7/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has: a fuse having one end applied with a first voltage, and a MOS transistor having source, gate and drain and a connection point between the other end of the fuse and one of the source and drain, a second voltage lower than the first voltage applied to the other of the source and drain, wherein: the first and second voltages, characteristics of the MOS transistor and a resistance of the fuse are selected so that the fuse can be broken down when a predetermined program voltage is applied to the gate; and the resistance of the fuse is set to such a value as a voltage difference between a voltage at the connection point and the second voltage is lower than a drain voltage of the MOS transistor at which a drain current starts saturating, when the program voltage is applied to the gate.
摘要翻译：半导体器件具有：具有施加第一电压的一端的熔丝和具有源极，栅极和漏极的MOS晶体管以及熔丝另一端与源极和漏极中的一个之间的连接点，第二电压低于施加到源极和漏极中的另一个的第一电压，其中：选择第一和第二电压，MOS晶体管的特性和熔丝的电阻，使得当将预定的编程电压施加到大门; 并且熔断器的电阻被设定为如下值：当连接点和第二电压之间的电压差低于漏极电流开始饱和的MOS晶体管的漏极电压时，当编程电压为应用于门。

4. 发明申请

US20050029621A1 Semiconductor device having fuse and its manufacture method 有权
标题翻译：具有保险丝的半导体器件及其制造方法
公开(公告)号：US20050029621A1
公开(公告)日：2005-02-10
申请号：US10935426
申请日：2004-09-08
申请人： Takayuki Kamiya , Masayoshi Omura
发明人： Takayuki Kamiya , Masayoshi Omura
IPC分类号： H01L21/82 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has: a fuse having one end applied with a first voltage, and a MOS transistor having source, gate and drain and a connection point between the other end of the fuse and one of the source and drain, a second voltage lower than the first voltage applied to the other of the source and drain, wherein: the first and second voltages, characteristics of the MOS transistor and a resistance of the fuse are selected so that the fuse can be broken down when a predetermined program voltage is applied to the gate; and the resistance of the fuse is set to such a value as a voltage difference between a voltage at the connection point and the second voltage is lower than a drain voltage of the MOS transistor at which a drain current starts saturating, when the program voltage is applied to the gate.
摘要翻译：半导体器件具有：具有施加第一电压的一端的熔丝和具有源极，栅极和漏极的MOS晶体管以及熔丝另一端与源极和漏极中的一个之间的连接点，第二电压低于施加到源极和漏极中的另一个的第一电压，其中：选择第一和第二电压，MOS晶体管的特性和熔丝的电阻，使得当将预定的编程电压施加到大门; 并且熔断器的电阻被设定为如下值：当连接点和第二电压之间的电压差低于漏极电流开始饱和的MOS晶体管的漏极电压时，当编程电压为应用于门。

5. 发明授权

US07180810B2 Method of breaking down a fuse in a semiconductor device 有权
标题翻译：分解半导体器件中的保险丝的方法
公开(公告)号：US07180810B2
公开(公告)日：2007-02-20
申请号：US11015030
申请日：2004-12-20
申请人： Takayuki Kamiya , Masayoshi Omura
发明人： Takayuki Kamiya , Masayoshi Omura
IPC分类号： G11C17/18 , G11C7/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has: a fuse having one end applied with a first voltage, and a MOS transistor having source, gate and drain and a connection point between the other end of the fuse and one of the source and drain, a second voltage lower than the first voltage applied to the other of the source and drain, wherein: the first and second voltages, characteristics of the MOS transistor and a resistance of the fuse are selected so that the fuse can be broken down when a predetermined program voltage is applied to the gate; and the resistance of the fuse is set to such a value as a voltage difference between a voltage at the connection point and the second voltage is lower than a drain voltage of the MOS transistor at which a drain current starts saturating, when the program voltage is applied to the gate.
摘要翻译：半导体器件具有：具有施加第一电压的一端的熔丝和具有源极，栅极和漏极的MOS晶体管以及熔丝另一端与源极和漏极中的一个之间的连接点，第二电压低于施加到源极和漏极中的另一个的第一电压，其中：选择第一和第二电压，MOS晶体管的特性和熔丝的电阻，使得当将预定的编程电压施加到大门; 并且熔断器的电阻被设定为如下值：当连接点和第二电压之间的电压差低于漏极电流开始饱和的MOS晶体管的漏极电压时，当编程电压为应用于门。

6. 发明授权

US08164120B2 Semiconductor device with capacitor and fuse and its manufacture 有权
标题翻译：具有电容器和保险丝的半导体器件及其制造
公开(公告)号：US08164120B2
公开(公告)日：2012-04-24
申请号：US12949637
申请日：2010-11-18
申请人： Masayoshi Omura
发明人： Masayoshi Omura
IPC分类号： H01L23/52
CPC分类号： H01L28/40 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.
摘要翻译：电容器的上电极具有第一和第二上电极的两层结构。通过构图用于形成电容器的下电极，第一上电极和第二上电极的导电层来形成MOS场效应晶体管的栅电极和熔丝。在通过常规方法在半导体衬底上形成电容器和熔丝时，选择性地使用至少三个蚀刻掩模来对各层进行图案化，以在布线连接之前形成电容器并熔断。在制造具有电容器，保险丝和MOS场效应晶体管的半导体器件中，可以减少蚀刻掩模的数量，从而可以减少工艺数量，并且容易提高生产率并降低制造成本。

7. 发明授权

US08138757B2 Manufacturing method for magnetic sensor and lead frame therefor 失效
标题翻译：磁传感器及其引线架的制造方法
公开(公告)号：US08138757B2
公开(公告)日：2012-03-20
申请号：US11214986
申请日：2005-08-31
申请人： Hiroshi Adachi , Hiroshi Saitoh , Kenichi Shirasaka , Hideki Sato , Masayoshi Omura
发明人： Hiroshi Adachi , Hiroshi Saitoh , Kenichi Shirasaka , Hideki Sato , Masayoshi Omura
IPC分类号： G01R33/02
CPC分类号： G01R33/0206 , G01C17/30 , H01L21/565 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01047 , H01L2924/01051 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/181 , Y10T29/49121 , Y10T29/49169 , Y10T29/49174 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are pressed, the interconnecting members are elastically deformed, so that the magnetic sensor chips are bonded onto the stages placed substantially in the same plane and are then wired with the leads. Thereafter, the stages are released from pressure, so that the interconnecting members are restored from the elastically deformed states thereof. When the magnetic sensor chips are combined together to realize three sensing directions, it is possible to accurately measure three-dimensional bearings of magnetism, and the magnetic sensor can be reduced in dimensions and manufactured with a reduced cost thereof.
摘要翻译：磁传感器由安装在由互连构件支撑的台架上的磁传感器芯片和在引线框架中具有引线的框架构成。这里，阶段倾向于互连构件的塑性变形。当框架保持在金属模具中并且阶段被按压时，互连构件弹性变形，使得磁性传感器芯片被接合到基本上位于同一平面上的台架上，然后与引线接线。此后，各级从压力释放，使互连构件从其弹性变形状态恢复。当磁传感器芯片组合在一起以实现三个感测方向时，可以精确地测量磁性的三维轴承，并且可以降低磁性传感器的尺寸并降低成本。

8. 发明授权

US07883466B2 Ultrasonic probe apparatus and ultrasonic diagnostic apparatus 有权
标题翻译：超声波探伤仪和超声波诊断仪
公开(公告)号：US07883466B2
公开(公告)日：2011-02-08
申请号：US11636678
申请日：2006-12-08
申请人： Hideo Adachi , Yoshiyjki Okuno , Akiko Mizunuma , Katsuhiro Wakabayashi , Takuya Imahashi , Yukihiko Sawada , Masayoshi Omura , Etsuko Omura, legal representative , Kozaburo Suzuki , Shuji Otani , Naomi Shimoda , Miyuki Murakami , Kiyoshi Nemoto
发明人： Hideo Adachi , Yoshiyjki Okuno , Akiko Mizunuma , Katsuhiro Wakabayashi , Takuya Imahashi , Yukihiko Sawada , Masayoshi Omura , Kozaburo Suzuki , Shuji Otani , Naomi Shimoda , Miyuki Murakami , Kiyoshi Nemoto
IPC分类号： A61B8/00
CPC分类号： A61B8/00 , A61B8/12 , A61B8/4483 , A61B8/4488 , A61B2562/028 , B06B1/0292 , G01S7/52026 , G01S15/8913 , G01S15/895 , G01S15/8963 , G01S15/8979
摘要： An ultrasonic probe apparatus which applies a RF pulse signal with a DC bias signal superimposed thereon to c-MUTs and transmits/receives an ultrasound wave is configured such that a transmission control system includes bias regulators which regulate the voltage value of the DC bias signal, a reception control system has a plurality of different frequency band pass filtering characteristics including at least those for a low pass and high pass and a frequency band pass filtering processing section which can select at least one frequency band pass filtering characteristic from those frequency band pass filtering characteristics. The apparatus controls voltage settings of the bias regulators in conjunction with the selection of frequency band pass filtering characteristics of the frequency band pass filtering processing section.
摘要翻译：将其上叠加有DC偏置信号的RF脉冲信号施加到c-MUT并发送/接收超声波的超声波探头装置被配置为使得传输控制系统包括调节DC偏置信号的电压值的偏置调节器，接收控制系统具有至少包括用于低通和高通的那些频带通滤波特性的多个不同的频带滤波特性，以及能够从这些频带滤波特性中选出至少一个频带滤波特性的频带滤波处理部特点该装置结合频带滤波处理部分的频带滤波特性的选择来控制偏置调节器的电压设置。

9. 发明申请

US20090033912A1 METHOD AND APPARATUS FOR READING IDENTIFICATION MARK ON SURFACE OF WAFER 有权
标题翻译：读取WAF表面识别标记的方法和装置
公开(公告)号：US20090033912A1
公开(公告)日：2009-02-05
申请号：US12145042
申请日：2008-06-24
申请人： Masaharu Sasaki , Masayoshi Omura
发明人： Masaharu Sasaki , Masayoshi Omura
IPC分类号： G01N21/00
CPC分类号： G06K9/2036
摘要： An identification mark constituted of irregularities is formed on the surface of a wafer, which is sealed with a resin layer and a dicing tape may be adhered to the backside. Multiple infrared units irradiate infrared rays towards the surface of the wafer from the backside thereof, wherein they transmit through the wafer and are then reflected at the interface between the resin layer and the surface of the wafer, thus producing reflected rays. An image pickup device picks up an image of the interface including the identification mark based on reflected rays. Optical axes of the infrared units extend to cross the surface of the wafer in different directions; hence, the image pickup device receives only a part of reflected rays, which are reflected at the interface in a prescribed direction. A polarizer can be arranged in proximity to the infrared unit or the image pickup device.
摘要翻译：在由树脂层密封的晶片的表面上形成由凹凸构成的识别标记，并且切割带可以粘附到背面。多个红外线单元从其背面向晶片的表面照射红外线，其中它们透过晶片，然后在树脂层与晶片表面之间的界面反射，从而产生反射光线。图像拾取装置基于反射光线拾取包括识别标记的界面的图像。红外单元的光轴延伸以在不同方向上跨越晶片的表面; 因此，图像拾取装置仅接收沿着规定方向在界面反射的反射光线的一部分。偏振器可以布置在靠近红外单元或图像拾取装置的位置。

10. 发明申请

US20090006020A1 COMPASS SENSOR UNIT AND PORTABLE ELECTRONIC DEVICE 失效
标题翻译： COMPASS传感器单元和便携式电子设备
公开(公告)号：US20090006020A1
公开(公告)日：2009-01-01
申请号：US12206521
申请日：2008-09-08
申请人： HIDEKI SATO , Yukio Wakui , Masayoshi Omura
发明人： HIDEKI SATO , Yukio Wakui , Masayoshi Omura
IPC分类号： G01C17/38
CPC分类号： G01C17/38
摘要： In a compass sensor unit, an azimuth data computing method is carried out by the steps of: inputting a signal from a geomagnetic sensor to measure magnetic field; determining whether to store measurement data of the magnetic field based on a distance from the last stored measurement data; calculating an offset value based on the stored data; making a comparison for each component of a plurality of measurement data used for calculating the offset value, and judging the offset value to be valid when a difference between the maximum and minimum values of each component is a given value or more; updating the already stored offset value to the offset value judged to be valid; and correcting newly provided measurement data by the updated offset value to compute azimuth data.
摘要翻译：在罗盘传感器单元中，通过以下步骤执行方位数据计算方法：输入来自地磁传感器的信号以测量磁场; 基于距离最后存储的测量数据的距离确定是否存储磁场的测量数据; 基于所存储的数据计算偏移值; 对用于计算偏移值的多个测量数据的每个分量进行比较，并且当每个分量的最大值和最小值之间的差是给定值或更大时，判断偏移值是有效的; 将已经存储的偏移值更新为判断为有效的偏移值; 并通过更新的偏移值对新提供的测量数据进行校正，以计算方位数据。

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